This patch fixes up the i82801dx_lpc.c code post transition.
Boot Tested (bootlog attached) Signed-off-by: Joseph Smith <joe@settoplinux.org> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5244 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
This commit is contained in:
Joseph Smith
Stefan Reinauer
parent
0d7a996695
commit
48f3e2b5e1
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@ -36,6 +36,9 @@
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extern void i82801dx_enable(device_t dev);
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#endif
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#define IO_APIC_ADDR 0xfec00000
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#define HPET_ADDR 0xfed00000
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#define DEBUG_PERIODIC_SMIS 0
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#define MAINBOARD_POWER_OFF 0
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@ -79,8 +82,15 @@ extern void i82801dx_enable(device_t dev);
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#define BIOS_CNTL 0x4E
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#define GPIO_BASE 0x58
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#define GPIO_CNTL 0x5C
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#define PIRQA_ROUT 0x60
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#define PIRQE_ROUT 0x68
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#define GPIOBASE_ADDR 0x0500
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#define PIRQA_ROUT 0x60
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#define PIRQB_ROUT 0x61
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#define PIRQC_ROUT 0x62
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#define PIRQD_ROUT 0x63
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#define PIRQE_ROUT 0x68
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#define PIRQF_ROUT 0x69
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#define PIRQG_ROUT 0x6A
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#define PIRQH_ROUT 0x6B
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#define COM_DEC 0xE0
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#define LPC_EN 0xE6
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#define FUNC_DIS 0xF2
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@ -192,4 +202,9 @@ extern void i82801dx_enable(device_t dev);
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#define TCOBASE 0x60 /* TCO Base Address Register */
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#define TCO1_CNT 0x08 /* TCO1 Control Register */
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/* GEN_PMCON_3 bits */
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#define RTC_BATTERY_DEAD (1 << 2)
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#define RTC_POWER_FAILED (1 << 1)
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#define SLEEP_AFTER_POWER_FAIL (1 << 0)
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#endif /* I82801DX_H */
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@ -4,6 +4,7 @@
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* Copyright (C) 2003 Linux Networx
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* Copyright (C) 2004 SuSE Linux AG
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* Copyright (C) 2004 Tyan Computer
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* Copyright (C) 2010 Joseph Smith <joe@settoplinux.org>
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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@ -32,128 +33,73 @@
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#define NMI_OFF 0
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void i82801dx_enable_ioapic(struct device *dev)
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typedef struct southbridge_intel_i82801dx_config config_t;
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static void i82801dx_enable_ioapic(struct device *dev)
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{
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u32 dword;
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volatile u32 *ioapic_sba = (volatile u32 *)0xfec00000;
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volatile u32 *ioapic_sbd = (volatile u32 *)0xfec00010;
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u32 reg32;
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volatile u32 *ioapic_index = (volatile u32 *)IO_APIC_ADDR;
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volatile u32 *ioapic_data = (volatile u32 *)IO_APIC_ADDR + 0x10;
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dword = pci_read_config32(dev, GEN_CNTL);
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dword |= (3 << 7); /* enable ioapic */
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dword |= (1 << 13); /* coprocessor error enable */
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dword |= (1 << 1); /* delay transaction enable */
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dword |= (1 << 2); /* DMA collection buf enable */
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pci_write_config32(dev, GEN_CNTL, dword);
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printk_debug("ioapic southbridge enabled %x\n", dword);
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*ioapic_sba = 0;
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*ioapic_sbd = (2 << 24);
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//lyh *ioapic_sba=3;
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//lyh *ioapic_sbd=1;
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*ioapic_sba = 0;
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dword = *ioapic_sbd;
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printk_debug("Southbridge apic id = %x\n", dword);
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if (dword != (2 << 24))
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die("");
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//lyh *ioapic_sba=3;
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//lyh dword=*ioapic_sbd;
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//lyh printk_debug("Southbridge apic DT = %x\n",dword);
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//lyh if(dword!=1)
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//lyh die("");
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/* Set ACPI base address (I/O space). */
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pci_write_config32(dev, PMBASE, (PMBASE_ADDR | 1));
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/* Enable ACPI I/O and power management. */
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pci_write_config8(dev, ACPI_CNTL, 0x10);
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reg32 = pci_read_config32(dev, GEN_CNTL);
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reg32 |= (3 << 7); /* Enable IOAPIC */
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reg32 |= (1 << 13); /* Coprocessor error enable */
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reg32 |= (1 << 1); /* Delayed transaction enable */
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reg32 |= (1 << 2); /* DMA collection buffer enable */
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pci_write_config32(dev, GEN_CNTL, reg32);
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printk_debug("IOAPIC Southbridge enabled %x\n", reg32);
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*ioapic_index = 0;
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*ioapic_data = (1 << 25);
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*ioapic_index = 0;
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reg32 = *ioapic_data;
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printk_debug("Southbridge APIC ID = %x\n", reg32);
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if (reg32 != (1 << 25))
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die("APIC Error\n");
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/* TODO: From i82801ca, needed/useful on other ICH? */
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*ioapic_index = 3; /* Select Boot Configuration register. */
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*ioapic_data = 1; /* Use Processor System Bus to deliver interrupts. */
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}
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void i82801dx_enable_serial_irqs(struct device *dev)
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static void i82801dx_enable_serial_irqs(struct device *dev)
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{
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/* Set packet length and toggle silent mode bit. */
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pci_write_config8(dev, SERIRQ_CNTL,
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(1 << 7) | (1 << 6) | ((21 - 17) << 2) | (0 << 0));
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pci_write_config8(dev, SERIRQ_CNTL,
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(1 << 7) | (0 << 6) | ((21 - 17) << 2) | (0 << 0));
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}
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void i82801dx_lpc_route_dma(struct device *dev, u8 mask)
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static void i82801dx_pirq_init(device_t dev)
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{
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u16 word;
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int i;
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word = pci_read_config16(dev, PCI_DMA_CFG);
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word &= ((1 << 10) - (1 << 8));
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for (i = 0; i < 8; i++) {
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if (i == 4)
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continue;
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word |= ((mask & (1 << i)) ? 3 : 1) << (i * 2);
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}
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pci_write_config16(dev, PCI_DMA_CFG, word);
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/* Get the chip configuration */
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config_t *config = dev->chip_info;
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pci_write_config8(dev, PIRQA_ROUT, config->pirqa_routing);
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pci_write_config8(dev, PIRQB_ROUT, config->pirqb_routing);
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pci_write_config8(dev, PIRQC_ROUT, config->pirqc_routing);
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pci_write_config8(dev, PIRQD_ROUT, config->pirqd_routing);
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pci_write_config8(dev, PIRQE_ROUT, config->pirqe_routing);
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pci_write_config8(dev, PIRQF_ROUT, config->pirqf_routing);
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pci_write_config8(dev, PIRQG_ROUT, config->pirqg_routing);
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pci_write_config8(dev, PIRQH_ROUT, config->pirqh_routing);
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}
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void i82801dx_rtc_init(struct device *dev)
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{
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u8 byte;
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u32 dword;
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int rtc_failed;
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byte = pci_read_config8(dev, GEN_PMCON_3);
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rtc_failed = byte & RTC_FAILED;
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if (rtc_failed) {
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byte &= ~(1 << 1); /* preserve the power fail state */
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pci_write_config8(dev, GEN_PMCON_3, byte);
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}
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dword = pci_read_config32(dev, GEN_STS);
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rtc_failed |= dword & (1 << 2);
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rtc_init(rtc_failed);
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}
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void i82801dx_1f0_misc(struct device *dev)
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{
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pci_write_config16(dev, PCICMD, 0x014f);
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pci_write_config32(dev, PMBASE, 0x00001001);
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pci_write_config8(dev, ACPI_CNTL, 0x10);
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pci_write_config32(dev, GPIO_BASE, 0x00001181);
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pci_write_config8(dev, GPIO_CNTL, 0x10);
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pci_write_config32(dev, PIRQA_ROUT, 0x0A05030B);
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pci_write_config8(dev, PIRQE_ROUT, 0x07);
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pci_write_config8(dev, RTC_CONF, 0x04);
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pci_write_config8(dev, COM_DEC, 0x10); //lyh E0->
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pci_write_config16(dev, LPC_EN, 0x000F); //LYH 000D->
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}
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static void enable_hpet(struct device *dev)
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{
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const unsigned long hpet_address = 0xfed00000;
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u32 dword;
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u32 code = (0 & 0x3);
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dword = pci_read_config32(dev, GEN_CNTL);
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dword |= (1 << 17); /* enable hpet */
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/*Bits [16:15]Memory Address Range
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00 FED0_0000h - FED0_03FFh
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01 FED0_1000h - FED0_13FFh
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10 FED0_2000h - FED0_23FFh
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11 FED0_3000h - FED0_33FFh */
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dword &= ~(3 << 15); /* clear it */
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dword |= (code << 15);
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printk_debug("enabling HPET @0x%lx\n", hpet_address | (code << 12));
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}
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static void lpc_init(struct device *dev)
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static void i82801dx_power_options(device_t dev)
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{
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u8 byte;
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int pwr_on = -1;
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int nmi_option;
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/* IO APIC initialization */
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i82801dx_enable_ioapic(dev);
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i82801dx_enable_serial_irqs(dev);
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#ifdef SUSPICIOUS_LOOKING_CODE
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// The ICH-4 datasheet does not mention this configuration register.
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// This code may have been inherited (incorrectly) from code for the AMD 766 southbridge,
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// which *does* support this functionality.
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/* posted memory write enable */
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byte = pci_read_config8(dev, 0x46);
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pci_write_config8(dev, 0x46, byte | (1 << 0));
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#endif
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/* power after power fail */
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/* FIXME this doesn't work! */
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/* Which state do we want to goto after g3 (power restored)?
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@ -161,37 +107,127 @@ static void lpc_init(struct device *dev)
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* 1 == S5 Soft Off
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*/
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pci_write_config8(dev, GEN_PMCON_3, pwr_on ? 0 : 1);
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printk_info("set power %s after power fail\n", pwr_on ? "on" : "off");
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#if 0
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/* Enable Error reporting */
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/* Set up sync flood detected */
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byte = pci_read_config8(dev, 0x47);
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byte |= (1 << 1);
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pci_write_config8(dev, 0x47, byte);
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#endif
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printk_info("Set power %s if power fails\n", pwr_on ? "on" : "off");
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/* Set up NMI on errors */
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/* Set up NMI on errors. */
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byte = inb(0x61);
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byte &= ~(1 << 3); /* IOCHK# NMI Enable */
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byte &= ~(1 << 2); /* PCI SERR# Enable */
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outb(byte, 0x61);
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byte = inb(0x70);
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nmi_option = NMI_OFF;
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get_option(&nmi_option, "nmi");
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if (nmi_option) {
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byte &= ~(1 << 7); /* set NMI */
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byte &= ~(1 << 7); /* Set NMI. */
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outb(byte, 0x70);
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}
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}
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/* Initialize the real time clock */
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static void gpio_init(device_t dev)
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{
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/* This should be done in romstage.c already */
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pci_write_config32(dev, GPIO_BASE, (GPIOBASE_ADDR | 1));
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pci_write_config8(dev, GPIO_CNTL, 0x10);
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}
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static void i82801dx_rtc_init(struct device *dev)
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{
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u8 reg8;
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u32 reg32;
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int rtc_failed;
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reg8 = pci_read_config8(dev, GEN_PMCON_3);
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rtc_failed = reg8 & RTC_BATTERY_DEAD;
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if (rtc_failed) {
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reg8 &= ~(1 << 1); /* Preserve the power fail state. */
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pci_write_config8(dev, GEN_PMCON_3, reg8);
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}
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reg32 = pci_read_config32(dev, GEN_STS);
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rtc_failed |= reg32 & (1 << 2);
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rtc_init(rtc_failed);
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/* Enable access to the upper 128 byte bank of CMOS RAM. */
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pci_write_config8(dev, RTC_CONF, 0x04);
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}
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static void i82801dx_lpc_route_dma(struct device *dev, u8 mask)
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{
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u16 reg16;
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int i;
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reg16 = pci_read_config16(dev, PCI_DMA_CFG);
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reg16 &= 0x300;
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for (i = 0; i < 8; i++) {
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if (i == 4)
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continue;
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reg16 |= ((mask & (1 << i)) ? 3 : 1) << (i * 2);
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}
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pci_write_config16(dev, PCI_DMA_CFG, reg16);
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}
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static void i82801dx_lpc_decode_en(device_t dev)
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{
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/* Decode 0x3F8-0x3FF (COM1) for COMA port, 0x2F8-0x2FF (COM2) for COMB.
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* LPT decode defaults to 0x378-0x37F and 0x778-0x77F.
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* Floppy decode defaults to 0x3F0-0x3F5, 0x3F7.
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* We also need to set the value for LPC I/F Enables Register.
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*/
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pci_write_config8(dev, COM_DEC, 0x10);
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pci_write_config16(dev, LPC_EN, 0x300F);
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}
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static void enable_hpet(struct device *dev)
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{
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u32 reg32;
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u32 code = (0 & 0x3);
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reg32 = pci_read_config32(dev, GEN_CNTL);
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reg32 |= (1 << 17); /* Enable HPET. */
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/*
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* Bits [16:15] Memory Address Range
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* 00 FED0_0000h - FED0_03FFh
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* 01 FED0_1000h - FED0_13FFh
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* 10 FED0_2000h - FED0_23FFh
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* 11 FED0_3000h - FED0_33FFh
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*/
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reg32 &= ~(3 << 15); /* Clear it */
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reg32 |= (code << 15);
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/* TODO: reg32 is never written to anywhere? */
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printk_debug("Enabling HPET @0x%x\n", HPET_ADDR | (code << 12));
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}
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static void lpc_init(struct device *dev)
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{
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/* Set the value for PCI command register. */
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pci_write_config16(dev, PCI_COMMAND, 0x000f);
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/* IO APIC initialization. */
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i82801dx_enable_ioapic(dev);
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i82801dx_enable_serial_irqs(dev);
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/* Setup the PIRQ. */
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i82801dx_pirq_init(dev);
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/* Setup power options. */
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i82801dx_power_options(dev);
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/* Set the state of the GPIO lines. */
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gpio_init(dev);
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/* Initialize the real time clock. */
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i82801dx_rtc_init(dev);
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/* Route DMA. */
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i82801dx_lpc_route_dma(dev, 0xff);
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/* Initialize isa dma */
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/* Initialize ISA DMA. */
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isa_dma_init();
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i82801dx_1f0_misc(dev);
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/* Setup decode ports and LPC I/F enables. */
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i82801dx_lpc_decode_en(dev);
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/* Initialize the High Precision Event Timers */
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enable_hpet(dev);
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}
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@ -208,15 +244,15 @@ static void i82801dx_lpc_read_resources(device_t dev)
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res->base = 0;
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res->size = 0x1000;
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res->flags = IORESOURCE_IO | IORESOURCE_SUBTRACTIVE |
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IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
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IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
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res = new_resource(dev, IOINDEX_SUBTRACTIVE(1, 0));
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res->base = 0xff800000;
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res->size = 0x00800000; /* 8 MB for flash */
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res->size = 0x00800000; /* 8 MB for flash */
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res->flags = IORESOURCE_MEM | IORESOURCE_SUBTRACTIVE |
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IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
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IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
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res = new_resource(dev, 3); /* IOAPIC */
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res = new_resource(dev, 3); /* IOAPIC */
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res->base = 0xfec00000;
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res->size = 0x00001000;
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res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
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@ -229,12 +265,12 @@ static void i82801dx_lpc_enable_resources(device_t dev)
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}
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static struct device_operations lpc_ops = {
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.read_resources = i82801dx_lpc_read_resources,
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.set_resources = pci_dev_set_resources,
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.enable_resources = i82801dx_lpc_enable_resources,
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.init = lpc_init,
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.scan_bus = scan_static_bus,
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.enable = i82801dx_enable,
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.read_resources = i82801dx_lpc_read_resources,
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.set_resources = pci_dev_set_resources,
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.enable_resources = i82801dx_lpc_enable_resources,
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.init = lpc_init,
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.scan_bus = scan_static_bus,
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.enable = i82801dx_enable,
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};
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/* 82801DB/DBL */
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