sb/intel/i82801jx: Use pmutil.h definitions
Also drop now-redundant definitions and include headers where needed. Tested with BUILD_TIMELESS=1, Intel DG43GT remains identical. Change-Id: I2fb46bb04d96df5e8261f49e0fd4d88eedca6084 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42659 Reviewed-by: Patrick Rudolph <siro@das-labor.org> Reviewed-by: Frans Hendriks <fhendriks@eltan.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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@ -5,6 +5,7 @@
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#include <device/smbus_host.h>
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#include <southbridge/intel/common/gpio.h>
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#include <southbridge/intel/common/pmbase.h>
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#include <southbridge/intel/common/pmutil.h>
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#include "i82801jx.h"
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#include "chip.h"
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@ -14,30 +14,6 @@
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#define APM_CNT 0xb2
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#define PM1_STS 0x00
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#define PWRBTN_STS (1 << 8)
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#define RTC_STS (1 << 10)
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#define PM1_EN 0x02
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#define PWRBTN_EN (1 << 8)
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#define GBL_EN (1 << 5)
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#define PM1_CNT 0x04
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#define SCI_EN (1 << 0)
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#define PM_LV2 0x14
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#define PM_LV3 0x15
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#define PM_LV4 0x16
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#define PM_LV5 0x17
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#define PM_LV6 0x18
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#define GPE0_STS 0x20
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#define SMI_EN 0x30
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#define PERIODIC_EN (1 << 14)
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#define TCO_EN (1 << 13)
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#define APMC_EN (1 << 5)
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#define BIOS_EN (1 << 2)
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#define EOS (1 << 1)
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#define GBL_SMI_EN (1 << 0)
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#define SMI_STS 0x34
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#define ALT_GP_SMI_EN 0x38
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#define ALT_GP_SMI_STS 0x3a
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#define GP_IO_USE_SEL 0x00
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@ -56,8 +32,6 @@
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#define MAINBOARD_POWER_KEEP 2
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/* D31:F0 LPC bridge */
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#define D31F0_PMBASE 0x40
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#define PMBASE D31F0_PMBASE
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#define D31F0_ACPI_CNTL 0x44
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#define ACPI_CNTL D31F0_ACPI_CNTL
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#define D31F0_GPIO_BASE 0x48
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@ -87,18 +61,11 @@
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#define D31F0_GEN2_DEC 0x88
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#define D31F0_GEN3_DEC 0x8c
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#define D31F0_GEN4_DEC 0x90
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#define D31F0_GEN_PMCON_1 0xa0
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#define D31F0_GEN_PMCON_3 0xa4
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#define D31F0_C5_EXIT_TIMING 0xa8
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#define D31F0_CxSTATE_CNF 0xa9
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#define D31F0_C4TIMING_CNT 0xaa
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#define D31F0_GPIO_ROUT 0xb8
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/* GEN_PMCON_3 bits */
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#define RTC_BATTERY_DEAD (1 << 2)
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#define RTC_POWER_FAILED (1 << 1)
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#define SLEEP_AFTER_POWER_FAIL (1 << 0)
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/* D31:F2 SATA */
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#define D31F2_IDE_TIM_PRI 0x40
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@ -21,6 +21,7 @@
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#include "i82801jx.h"
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#include "nvs.h"
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#include <southbridge/intel/common/pciehp.h>
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#include <southbridge/intel/common/pmutil.h>
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#include <southbridge/intel/common/acpi_pirq_gen.h>
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#define NMI_OFF 0
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