soc/intel/tigerlake: Enable VT-d and generate DMAR ACPI table
Tigerlake platform supports Virtualization Technology for Directed I/O. Enable VT-d feature and generate DMAR ACPI table. BUG=None TEST=Booted to kernel and "dmesg | grep DMAR" to verify the DMAR ACPI remapping table existence. Retrieve /sys/firmware/acpi/tables/DMAR and "iasl -d DMAR" to check all entries. Change-Id: Ib89d0835385487735c63062a084794d9da19605e Signed-off-by: John Zhao <john.zhao@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38165 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com>
This commit is contained in:
John Zhao
Patrick Georgi
parent
a7ec42619c
commit
49111cd2ba
6 changed files with 174 additions and 3 deletions
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@ -18,6 +18,8 @@
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#include <device/mmio.h>
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#include <arch/smp/mpspec.h>
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#include <cbmem.h>
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#include <console/console.h>
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#include <device/pci_ops.h>
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#include <ec/google/chromeec/ec.h>
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#include <intelblocks/cpulib.h>
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#include <intelblocks/pmclib.h>
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@ -191,6 +193,98 @@ uint32_t soc_read_sci_irq_select(void)
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return read32((void *)pmc_bar + IRQ_REG);
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}
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static unsigned long soc_fill_dmar(unsigned long current)
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{
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const struct device *const igfx_dev = pcidev_path_on_root(SA_DEVFN_IGD);
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uint64_t gfxvtbar = MCHBAR64(GFXVTBAR) & VTBAR_MASK;
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bool gfxvten = MCHBAR32(GFXVTBAR) & VTBAR_ENABLED;
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if (igfx_dev && igfx_dev->enabled && gfxvtbar && gfxvten) {
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unsigned long tmp = current;
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current += acpi_create_dmar_drhd(current, 0, 0, gfxvtbar);
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current += acpi_create_dmar_ds_pci(current, 0, 2, 0);
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acpi_dmar_drhd_fixup(tmp, current);
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}
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const struct device *const ipu_dev = pcidev_path_on_root(SA_DEVFN_IPU);
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uint64_t ipuvtbar = MCHBAR64(IPUVTBAR) & VTBAR_MASK;
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bool ipuvten = MCHBAR32(IPUVTBAR) & VTBAR_ENABLED;
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if (ipu_dev && ipu_dev->enabled && ipuvtbar && ipuvten) {
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unsigned long tmp = current;
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current += acpi_create_dmar_drhd(current, 0, 0, ipuvtbar);
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current += acpi_create_dmar_ds_pci(current, 0, 5, 0);
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acpi_dmar_drhd_fixup(tmp, current);
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}
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uint64_t vtvc0bar = MCHBAR64(VTVC0BAR) & VTBAR_MASK;
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bool vtvc0en = MCHBAR32(VTVC0BAR) & VTBAR_ENABLED;
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if (vtvc0bar && vtvc0en) {
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const unsigned long tmp = current;
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current += acpi_create_dmar_drhd(current,
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DRHD_INCLUDE_PCI_ALL, 0, vtvc0bar);
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current += acpi_create_dmar_ds_ioapic(current,
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2, V_P2SB_CFG_IBDF_BUS, V_P2SB_CFG_IBDF_DEV,
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V_P2SB_CFG_IBDF_FUNC);
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current += acpi_create_dmar_ds_msi_hpet(current,
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0, V_P2SB_CFG_HBDF_BUS, V_P2SB_CFG_HBDF_DEV,
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V_P2SB_CFG_HBDF_FUNC);
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acpi_dmar_drhd_fixup(tmp, current);
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}
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/* TCSS Thunderbolt root ports */
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for (unsigned int i = 0; i < MAX_TBT_PCIE_PORT; i++) {
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uint64_t tbtbar = MCHBAR64(TBT0BAR + i * 8) & VTBAR_MASK;
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bool tbten = MCHBAR32(TBT0BAR + i * 8) & VTBAR_ENABLED;
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if (tbtbar && tbten) {
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unsigned long tmp = current;
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current += acpi_create_dmar_drhd(current, 0, 0, tbtbar);
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current += acpi_create_dmar_ds_pci(current, 0, 7, i);
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acpi_dmar_drhd_fixup(tmp, current);
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}
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}
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/* Add RMRR entry */
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const unsigned long tmp = current;
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current += acpi_create_dmar_rmrr(current, 0,
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sa_get_gsm_base(), sa_get_tolud_base() - 1);
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current += acpi_create_dmar_ds_pci(current, 0, 2, 0);
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acpi_dmar_rmrr_fixup(tmp, current);
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return current;
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}
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unsigned long sa_write_acpi_tables(struct device *dev, unsigned long current,
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struct acpi_rsdp *rsdp)
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{
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acpi_dmar_t *const dmar = (acpi_dmar_t *)current;
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/*
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* Create DMAR table only if we have VT-d capability and FSP does not override its
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* feature.
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*/
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if ((pci_read_config32(dev, CAPID0_A) & VTD_DISABLE) ||
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!(MCHBAR32(VTVC0BAR) & VTBAR_ENABLED))
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return current;
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printk(BIOS_DEBUG, "ACPI: * DMAR\n");
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acpi_create_dmar(dmar, DMAR_INTR_REMAP | DMA_CTRL_PLATFORM_OPT_IN_FLAG, soc_fill_dmar);
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current += dmar->header.length;
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current = acpi_align_current(current);
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acpi_add_table(rsdp, dmar);
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return current;
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}
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void acpi_create_gnvs(struct global_nvs_t *gnvs)
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{
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config_t *config = config_of_soc();
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@ -51,6 +51,27 @@
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#define EDRAM_BASE_ADDRESS 0xfed80000
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#define EDRAM_BASE_SIZE 0x4000
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#define TBT0_BASE_ADDRESS 0xfed84000
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#define TBT0_BASE_SIZE 0x1000
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#define TBT1_BASE_ADDRESS 0xfed85000
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#define TBT1_BASE_SIZE 0x1000
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#define TBT2_BASE_ADDRESS 0xfed86000
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#define TBT2_BASE_SIZE 0x1000
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#define TBT3_BASE_ADDRESS 0xfed87000
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#define TBT3_BASE_SIZE 0x1000
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#define GFXVT_BASE_ADDRESS 0xfed90000
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#define GFXVT_BASE_SIZE 0x1000
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#define IPUVT_BASE_ADDRESS 0xfed92000
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#define IPUVT_BASE_SIZE 0x1000
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#define VTVC0_BASE_ADDRESS 0xfed91000
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#define VTVC0_BASE_SIZE 0x1000
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#define REG_BASE_ADDRESS 0xfb000000
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#define REG_BASE_SIZE 0x1000
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@ -1,7 +1,7 @@
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/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2019 Intel Corporation.
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* Copyright (C) 2019-2020 Intel Corporation.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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@ -53,6 +53,10 @@
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#define SA_DEV_TBT2 PCI_DEV(0, SA_DEV_SLOT_TBT, 2)
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#define SA_DEV_TBT3 PCI_DEV(0, SA_DEV_SLOT_TBT, 3)
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#define SA_DEV_SLOT_IPU 0x05
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#define SA_DEVFN_IPU PCI_DEVFN(SA_DEV_SLOT_IPU, 0)
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#define SA_DEV_IPU PCI_DEV(0, SA_DEV_SLOT_IPU, 0)
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/* PCH Devices */
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#define PCH_DEV_SLOT_SIO0 0x10
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#define PCH_DEVFN_CNVI_BT _PCH_DEVFN(SIO0, 2)
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@ -1,7 +1,7 @@
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/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2019 Intel Corporation.
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* Copyright (C) 2019-2020 Intel Corporation.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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@ -34,10 +34,23 @@
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#define D_LCK (1 << 4)
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#define G_SMRAME (1 << 3)
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#define C_BASE_SEG ((0 << 2) | (1 << 1) | (0 << 0))
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#define CAPID0_A 0xe4
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#define VTD_DISABLE (1 << 23)
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#define BIOS_RESET_CPL 0x5da8
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#define GFXVTBAR 0x5400
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#define EDRAMBAR 0x5408
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#define VTVC0BAR 0x5410
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#define REGBAR 0x5420
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#define IPUVTBAR 0x7880
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#define TBT0BAR 0x7888
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#define TBT1BAR 0x7890
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#define TBT2BAR 0x7898
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#define TBT3BAR 0x78A0
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#define MAX_TBT_PCIE_PORT 4
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#define VTBAR_ENABLED 0x01
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#define VTBAR_MASK 0x7ffffff000ull
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#define MCH_PKG_POWER_LIMIT_LO 0x59a0
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#define MCH_PKG_POWER_LIMIT_HI 0x59a4
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@ -47,4 +60,21 @@
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#define IMRBASE 0x6A40
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#define IMRLIMIT 0x6A48
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static const struct sa_mmio_descriptor soc_vtd_resources[] = {
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{ GFXVTBAR, GFXVT_BASE_ADDRESS, GFXVT_BASE_SIZE, "GFXVTBAR" },
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{ IPUVTBAR, IPUVT_BASE_ADDRESS, IPUVT_BASE_SIZE, "IPUVTBAR" },
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{ TBT0BAR, TBT0_BASE_ADDRESS, TBT0_BASE_SIZE, "TBT0BAR" },
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{ TBT1BAR, TBT1_BASE_ADDRESS, TBT1_BASE_SIZE, "TBT1BAR" },
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{ TBT2BAR, TBT2_BASE_ADDRESS, TBT2_BASE_SIZE, "TBT2BAR" },
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{ TBT3BAR, TBT3_BASE_ADDRESS, TBT3_BASE_SIZE, "TBT3BAR" },
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{ VTVC0BAR, VTVC0_BASE_ADDRESS, VTVC0_BASE_SIZE, "VTVC0BAR" },
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};
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#define V_P2SB_CFG_IBDF_BUS 0
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#define V_P2SB_CFG_IBDF_DEV 30
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#define V_P2SB_CFG_IBDF_FUNC 7
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#define V_P2SB_CFG_HBDF_BUS 0
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#define V_P2SB_CFG_HBDF_DEV 30
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#define V_P2SB_CFG_HBDF_FUNC 6
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#endif
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@ -131,6 +131,20 @@ static void soc_memory_init_params(FSP_M_CONFIG *m_cfg,
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m_cfg->PchHdaIDispLinkTmode = config->PchHdaIDispLinkTmode;
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m_cfg->PchHdaIDispLinkFrequency = config->PchHdaIDispLinkFrequency;
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m_cfg->PchHdaIDispCodecDisconnect = config->PchHdaIDispCodecDisconnect;
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/* Vt-D config */
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m_cfg->VtdDisable = 0;
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m_cfg->VtdIgdEnable = 0x1;
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m_cfg->VtdBaseAddress[0] = GFXVT_BASE_ADDRESS;
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m_cfg->VtdIpuEnable = 0x1;
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m_cfg->VtdBaseAddress[1] = IPUVT_BASE_ADDRESS;
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m_cfg->VtdIopEnable = 0x1;
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m_cfg->VtdBaseAddress[2] = VTVC0_BASE_ADDRESS;
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m_cfg->VtdItbtEnable = 0x1;
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m_cfg->VtdBaseAddress[3] = TBT0_BASE_ADDRESS;
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m_cfg->VtdBaseAddress[4] = TBT1_BASE_ADDRESS;
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m_cfg->VtdBaseAddress[5] = TBT2_BASE_ADDRESS;
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m_cfg->VtdBaseAddress[6] = TBT3_BASE_ADDRESS;
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}
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void platform_fsp_memory_init_params_cb(FSPM_UPD *mupd, uint32_t version)
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@ -1,7 +1,7 @@
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/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2019 Intel Corp.
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* Copyright (C) 2019-2020 Intel Corp.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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@ -21,6 +21,7 @@
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#include <device/device.h>
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#include <device/pci.h>
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#include <device/pci_ops.h>
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#include <intelblocks/systemagent.h>
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#include <soc/iomap.h>
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#include <soc/systemagent.h>
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@ -56,6 +57,13 @@ void soc_add_fixed_mmio_resources(struct device *dev, int *index)
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sa_add_fixed_mmio_resources(dev, index, soc_fixed_resources,
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ARRAY_SIZE(soc_fixed_resources));
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/* Add Vt-d resources if VT-d is enabled */
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if ((pci_read_config32(dev, CAPID0_A) & VTD_DISABLE))
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return;
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sa_add_fixed_mmio_resources(dev, index, soc_vtd_resources,
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ARRAY_SIZE(soc_vtd_resources));
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}
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/*
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