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cpu/x86/smm: Define single smm_subregion() 

At the moment we only have two splitting of TSEG,
one with and one without IED. They can all use
same implementation.

Make configuration problems of TSEG region assertion
failures.

Rename file from stage_cache.c to tseg_region.c to
reflect it's purpose.

Change-Id: I9daf0dec8fbaaa1f4e6004ea034869f43412d7d5
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34776
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: David Guckian
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Kyösti Mälkki 2019-08-05 12:49:09 +03:00
parent b1af16a424
commit 4913d8aed0
11 changed files with 95 additions and 339 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

6
src/cpu/x86/smm/Makefile.inc
View File

@ -42,9 +42,9 @@ endif
ifeq ($(CONFIG_SMM_TSEG),y) ifeq ($(CONFIG_SMM_TSEG),y)
ramstage-y += stage_cache.c ramstage-y += tseg_region.c
romstage-y += stage_cache.c romstage-y += tseg_region.c
postcar-y += stage_cache.c postcar-y += tseg_region.c
smmstub-y += smm_stub.S smmstub-y += smm_stub.S

33
src/cpu/x86/smm/stage_cache.c
View File

@ -1,33 +0,0 @@
/*
* This file is part of the coreboot project.
*
* Copyright 2013 Google Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#include <console/console.h>
#include <cpu/x86/smm.h>
#include <stage_cache.h>
#include <types.h>
int __weak smm_subregion(int sub, uintptr_t *base, size_t *size)
{
return -1;
}
void __weak stage_cache_external_region(void **base, size_t *size)
{
if (smm_subregion(SMM_SUBREGION_CACHE, (uintptr_t *)base, size)) {
printk(BIOS_ERR, "ERROR: No cache SMM subregion.\n");
*base = NULL;
*size = 0;
}
}

86
src/cpu/x86/smm/tseg_region.c Normal file
View File

@ -0,0 +1,86 @@
/*
* This file is part of the coreboot project.
*
* Copyright 2013 Google Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#include <assert.h>
#include <commonlib/helpers.h>
#include <console/console.h>
#include <cpu/x86/smm.h>
#include <stage_cache.h>
#include <types.h>
void __weak smm_region(uintptr_t *start, size_t *size)
{
*start = 0;
*size = 0;
}
/*
* Subregions within SMM
* +-------------------------+
* | IED | IED_REGION_SIZE
* +-------------------------+
* | External Stage Cache | SMM_RESERVED_SIZE
* +-------------------------+
* | code and data |
* | (TSEG) |
* +-------------------------+ TSEG
*/
int smm_subregion(int sub, uintptr_t *start, size_t *size)
{
uintptr_t sub_base;
size_t sub_size;
const size_t ied_size = CONFIG_IED_REGION_SIZE;
const size_t cache_size = CONFIG_SMM_RESERVED_SIZE;
smm_region(&sub_base, &sub_size);
ASSERT(IS_ALIGNED(sub_base, sub_size));
ASSERT(sub_size > (cache_size + ied_size));
switch (sub) {
case SMM_SUBREGION_HANDLER:
/* Handler starts at the base of TSEG. */
sub_size -= ied_size;
sub_size -= cache_size;
break;
case SMM_SUBREGION_CACHE:
/* External cache is in the middle of TSEG. */
sub_base += sub_size - (ied_size + cache_size);
sub_size = cache_size;
break;
case SMM_SUBREGION_CHIPSET:
/* IED is at the top. */
sub_base += sub_size - ied_size;
sub_size = ied_size;
break;
default:
*start = 0;
*size = 0;
return -1;
}
*start = sub_base;
*size = sub_size;
return 0;
}
void __weak stage_cache_external_region(void **base, size_t *size)
{
if (smm_subregion(SMM_SUBREGION_CACHE, (uintptr_t *)base, size)) {
printk(BIOS_ERR, "ERROR: No cache SMM subregion.\n");
*base = NULL;
*size = 0;
}
}

36
src/soc/amd/picasso/ramtop.c
View File

@ -81,12 +81,6 @@ static size_t smm_region_size(void)
return CONFIG_SMM_TSEG_SIZE; return CONFIG_SMM_TSEG_SIZE;
} }
void smm_region(uintptr_t *start, size_t *size)
{
*start = smm_region_start();
*size = smm_region_size();
}
/* /*
* For data stored in TSEG, ensure TValid is clear so R/W access can reach * For data stored in TSEG, ensure TValid is clear so R/W access can reach
* the DRAM when not in SMM. * the DRAM when not in SMM.
@ -109,39 +103,15 @@ static void clear_tvalid(void)
wrmsr(SMM_MASK_MSR, mask); wrmsr(SMM_MASK_MSR, mask);
} }
int smm_subregion(int sub, uintptr_t *start, size_t *size) void smm_region(uintptr_t *start, size_t *size)
{ {
static int once; static int once;
uintptr_t sub_base;
size_t sub_size;
const size_t cache_size = CONFIG_SMM_RESERVED_SIZE;
smm_region(&sub_base, &sub_size); *start = smm_region_start();
assert(sub_size > CONFIG_SMM_RESERVED_SIZE); *size = smm_region_size();
if (!once) { if (!once) {
clear_tvalid(); clear_tvalid();
once = 1; once = 1;
} }
switch (sub) {
case SMM_SUBREGION_HANDLER:
/* Handler starts at the base of TSEG. */
sub_size -= cache_size;
break;
case SMM_SUBREGION_CACHE:
/* External cache is in the middle of TSEG. */
sub_base += sub_size - cache_size;
sub_size = cache_size;
break;
default:
*start = 0;
*size = 0;
return -1;
}
*start = (void *)sub_base;
*size = sub_size;
return 0;
} }

35
src/soc/amd/stoneyridge/ramtop.c
View File

@ -81,12 +81,6 @@ static size_t smm_region_size(void)
return CONFIG_SMM_TSEG_SIZE; return CONFIG_SMM_TSEG_SIZE;
} }
void smm_region(uintptr_t *start, size_t *size)
{
*start = smm_region_start();
*size = smm_region_size();
}
/* /*
* For data stored in TSEG, ensure TValid is clear so R/W access can reach * For data stored in TSEG, ensure TValid is clear so R/W access can reach
* the DRAM when not in SMM. * the DRAM when not in SMM.
@ -109,38 +103,15 @@ static void clear_tvalid(void)
wrmsr(SMM_MASK_MSR, mask); wrmsr(SMM_MASK_MSR, mask);
} }
int smm_subregion(int sub, uintptr_t *start, size_t *size) void smm_region(uintptr_t *start, size_t *size)
{ {
static int once; static int once;
uintptr_t sub_base;
size_t sub_size;
const size_t cache_size = CONFIG_SMM_RESERVED_SIZE;
smm_region(&sub_base, &sub_size); *start = smm_region_start();
assert(sub_size > CONFIG_SMM_RESERVED_SIZE); *size = smm_region_size();
if (!once) { if (!once) {
clear_tvalid(); clear_tvalid();
once = 1; once = 1;
} }
switch (sub) {
case SMM_SUBREGION_HANDLER:
/* Handler starts at the base of TSEG. */
sub_size -= cache_size;
break;
case SMM_SUBREGION_CACHE:
/* External cache is in the middle of TSEG. */
sub_base += sub_size - cache_size;
sub_size = cache_size;
break;
default:
*start = 0;
*size = 0;
return -1;
}
*start = sub_base;
*size = sub_size;
return 0;
} }

29
src/soc/intel/apollolake/memmap.c
View File

@ -48,32 +48,3 @@ void smm_region(uintptr_t *start, size_t *size)
*start = sa_get_tseg_base(); *start = sa_get_tseg_base();
*size = sa_get_tseg_size(); *size = sa_get_tseg_size();
} }
int smm_subregion(int sub, uintptr_t *start, size_t *size)
{
uintptr_t sub_base;
size_t sub_size;
const size_t cache_size = CONFIG_SMM_RESERVED_SIZE;
smm_region(&sub_base, &sub_size);
switch (sub) {
case SMM_SUBREGION_HANDLER:
/* Handler starts at the base of TSEG. */
sub_size -= cache_size;
break;
case SMM_SUBREGION_CACHE:
/* External cache is in the middle of TSEG. */
sub_base += sub_size - cache_size;
sub_size = cache_size;
break;
default:
*start = 0;
*size = 0;
return -1;
}
*start = sub_base;
*size = sub_size;
return 0;
}

38
src/soc/intel/braswell/memmap.c
View File

@ -34,44 +34,6 @@ void smm_region(uintptr_t *start, size_t *size)
*size = smm_region_size(); *size = smm_region_size();
} }
/*
* Subregions within SMM
* +-------------------------+ BUNIT_SMRRH
* | External Stage Cache | SMM_RESERVED_SIZE
* +-------------------------+
* | code and data |
* | (TSEG) |
* +-------------------------+ BUNIT_SMRRL
*/
int smm_subregion(int sub, uintptr_t *start, size_t *size)
{
uintptr_t sub_base;
size_t sub_size;
const size_t cache_size = CONFIG_SMM_RESERVED_SIZE;
smm_region(&sub_base, &sub_size);
switch (sub) {
case SMM_SUBREGION_HANDLER:
/* Handler starts at the base of TSEG. */
sub_size -= cache_size;
break;
case SMM_SUBREGION_CACHE:
/* External cache is in the middle of TSEG. */
sub_base += sub_size - cache_size;
sub_size = cache_size;
break;
default:
*start = 0;
*size = 0;
return -1;
}
*start = sub_base;
*size = sub_size;
return 0;
}
void *cbmem_top(void) void *cbmem_top(void)
{ {
uintptr_t smm_base; uintptr_t smm_base;

47
src/soc/intel/cannonlake/memmap.c
View File

@ -35,53 +35,6 @@ void smm_region(uintptr_t *start, size_t *size)
*size = sa_get_tseg_size(); *size = sa_get_tseg_size();
} }
/*
* Subregions within SMM
* +-------------------------+ BGSM
* | IED | IED_REGION_SIZE
* +-------------------------+
* | External Stage Cache | SMM_RESERVED_SIZE
* +-------------------------+
* | code and data |
* | (TSEG) |
* +-------------------------+ TSEG
*/
int smm_subregion(int sub, uintptr_t *start, size_t *size)
{
uintptr_t sub_base;
size_t sub_size;
const size_t ied_size = CONFIG_IED_REGION_SIZE;
const size_t cache_size = CONFIG_SMM_RESERVED_SIZE;
smm_region(&sub_base, &sub_size);
switch (sub) {
case SMM_SUBREGION_HANDLER:
/* Handler starts at the base of TSEG. */
sub_size -= ied_size;
sub_size -= cache_size;
break;
case SMM_SUBREGION_CACHE:
/* External cache is in the middle of TSEG. */
sub_base += sub_size - (ied_size + cache_size);
sub_size = cache_size;
break;
case SMM_SUBREGION_CHIPSET:
/* IED is at the top. */
sub_base += sub_size - ied_size;
sub_size = ied_size;
break;
default:
*start = 0;
*size = 0;
return -1;
}
*start = sub_base;
*size = sub_size;
return 0;
}
/* Calculate ME Stolen size */ /* Calculate ME Stolen size */
static size_t get_imr_size(void) static size_t get_imr_size(void)
{ {

30
src/soc/intel/denverton_ns/memmap.c
View File

@ -75,33 +75,3 @@ void smm_region(uintptr_t *start, size_t *size)
*start = smm_region_start(); *start = smm_region_start();
*size = smm_region_size(); *size = smm_region_size();
} }
int smm_subregion(int sub, uintptr_t *start, size_t *size)
{
uintptr_t sub_base;
size_t sub_size;
const size_t cache_size = CONFIG_SMM_RESERVED_SIZE;
smm_region(&sub_base, &sub_size);
assert(sub_size > CONFIG_SMM_RESERVED_SIZE);
switch (sub) {
case SMM_SUBREGION_HANDLER:
/* Handler starts at the base of TSEG. */
sub_size -= cache_size;
break;
case SMM_SUBREGION_CACHE:
/* External cache is in the middle of TSEG. */
sub_base += sub_size - cache_size;
sub_size = cache_size;
break;
default:
*start = 0;
*size = 0;
return -1;
}
*start = sub_base;
*size = sub_size;
return 0;
}

47
src/soc/intel/icelake/memmap.c
View File

@ -33,53 +33,6 @@ void smm_region(uintptr_t *start, size_t *size)
*size = sa_get_tseg_size(); *size = sa_get_tseg_size();
} }
/*
* Subregions within SMM
* +-------------------------+ BGSM
* | IED | IED_REGION_SIZE
* +-------------------------+
* | External Stage Cache | SMM_RESERVED_SIZE
* +-------------------------+
* | code and data |
* | (TSEG) |
* +-------------------------+ TSEG
*/
int smm_subregion(int sub, uintptr_t *start, size_t *size)
{
uintptr_t sub_base;
size_t sub_size;
const size_t ied_size = CONFIG_IED_REGION_SIZE;
const size_t cache_size = CONFIG_SMM_RESERVED_SIZE;
smm_region(&sub_base, &sub_size);
switch (sub) {
case SMM_SUBREGION_HANDLER:
/* Handler starts at the base of TSEG. */
sub_size -= ied_size;
sub_size -= cache_size;
break;
case SMM_SUBREGION_CACHE:
/* External cache is in the middle of TSEG. */
sub_base += sub_size - (ied_size + cache_size);
sub_size = cache_size;
break;
case SMM_SUBREGION_CHIPSET:
/* IED is at the top. */
sub_base += sub_size - ied_size;
sub_size = ied_size;
break;
default:
*start = 0;
*size = 0;
return -1;
}
*start = sub_base;
*size = sub_size;
return 0;
}
/* Calculate ME Stolen size */ /* Calculate ME Stolen size */
static size_t get_imr_size(void) static size_t get_imr_size(void)
{ {

47
src/soc/intel/skylake/memmap.c
View File

@ -37,53 +37,6 @@ void smm_region(uintptr_t *start, size_t *size)
*size = sa_get_tseg_size(); *size = sa_get_tseg_size();
} }
/*
* Subregions within SMM
* +-------------------------+ BGSM
* | IED | IED_REGION_SIZE
* +-------------------------+
* | External Stage Cache | SMM_RESERVED_SIZE
* +-------------------------+
* | code and data |
* | (TSEG) |
* +-------------------------+ TSEG
*/
int smm_subregion(int sub, uintptr_t *start, size_t *size)
{
uintptr_t sub_base;
size_t sub_size;
const size_t ied_size = CONFIG_IED_REGION_SIZE;
const size_t cache_size = CONFIG_SMM_RESERVED_SIZE;
smm_region(&sub_base, &sub_size);
switch (sub) {
case SMM_SUBREGION_HANDLER:
/* Handler starts at the base of TSEG. */
sub_size -= ied_size;
sub_size -= cache_size;
break;
case SMM_SUBREGION_CACHE:
/* External cache is in the middle of TSEG. */
sub_base += sub_size - (ied_size + cache_size);
sub_size = cache_size;
break;
case SMM_SUBREGION_CHIPSET:
/* IED is at the top. */
sub_base += sub_size - ied_size;
sub_size = ied_size;
break;
default:
*start = 0;
*size = 0;
return -1;
}
*start = sub_base;
*size = sub_size;
return 0;
}
static bool is_ptt_enable(void) static bool is_ptt_enable(void)
{ {
if ((read32((void *)PTT_TXT_BASE_ADDRESS) & PTT_PRESENT) == if ((read32((void *)PTT_TXT_BASE_ADDRESS) & PTT_PRESENT) ==