soc/intel/apollolake: Add cbmem_top() implementation
On Apollolake CPU memory mapping is similar to previous SoC, and we place CBMEM right under TSEG. Change-Id: I606f690449ba98af6e9fc3074d677c7287892164 Signed-off-by: Andrey Petrov <andrey.petrov@intel.com> Reviewed-on: https://review.coreboot.org/13883 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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@ -20,12 +20,14 @@ romstage-y += placeholders.c
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romstage-$(CONFIG_PLATFORM_USES_FSP2_0) += romstage.c
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romstage-y += gpio.c
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romstage-$(CONFIG_SOC_UART_DEBUG) += uart_early.c
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romstage-y += memmap.c
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romstage-y += mmap_boot.c
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smm-y += placeholders.c
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ramstage-y += placeholders.c
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ramstage-y += gpio.c
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ramstage-$(CONFIG_SOC_UART_DEBUG) += uart_early.c
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ramstage-y += memmap.c
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ramstage-y += mmap_boot.c
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CPPFLAGS_common += -I$(src)/soc/intel/apollolake/include
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@ -0,0 +1,27 @@
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/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2015 Intel Corp.
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* (Written by Andrey Petrov <andrey.petrov@intel.com> for Intel Corp.)
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*/
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#include <arch/io.h>
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#include <cbmem.h>
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#include <device/pci.h>
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#include <soc/northbridge.h>
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#include <soc/pci_devs.h>
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static uintptr_t smm_region_start(void)
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{
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return ALIGN_DOWN(pci_read_config32(NB_DEV_ROOT, TSEG), 1*MiB);
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}
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void *cbmem_top(void)
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{
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return (void *)smm_region_start();
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}
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@ -3,11 +3,6 @@
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#include <delay.h>
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#include <rules.h>
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void *cbmem_top(void)
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{
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return NULL;
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}
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void southbridge_smi_set_eos(void)
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{
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}
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