soc/intel/apollolake: Add cbmem_top() implementation

On Apollolake CPU memory mapping is similar to previous SoC, and
we place CBMEM right under TSEG.

Change-Id: I606f690449ba98af6e9fc3074d677c7287892164
Signed-off-by: Andrey Petrov <andrey.petrov@intel.com>
Reviewed-on: https://review.coreboot.org/13883
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>

src/soc/intel/apollolake/Makefile.inc

@@ -20,12 +20,14 @@ romstage-y += placeholders.c
 romstage-$(CONFIG_PLATFORM_USES_FSP2_0) += romstage.c
 romstage-y += gpio.c
 romstage-$(CONFIG_SOC_UART_DEBUG) += uart_early.c
+romstage-y += memmap.c
 romstage-y += mmap_boot.c
 
 smm-y += placeholders.c
 ramstage-y += placeholders.c
 ramstage-y += gpio.c
 ramstage-$(CONFIG_SOC_UART_DEBUG) += uart_early.c
+ramstage-y += memmap.c
 ramstage-y += mmap_boot.c
 
 CPPFLAGS_common += -I$(src)/soc/intel/apollolake/include

src/soc/intel/apollolake/memmap.c

@@ -0,0 +1,27 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2015 Intel Corp.
+ * (Written by Andrey Petrov <andrey.petrov@intel.com> for Intel Corp.)
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+
+#include <arch/io.h>
+#include <cbmem.h>
+#include <device/pci.h>
+#include <soc/northbridge.h>
+#include <soc/pci_devs.h>
+
+static uintptr_t smm_region_start(void)
+{
+	return ALIGN_DOWN(pci_read_config32(NB_DEV_ROOT, TSEG), 1*MiB);
+}
+
+void *cbmem_top(void)
+{
+	return (void *)smm_region_start();
+}

src/soc/intel/apollolake/placeholders.c

@@ -3,11 +3,6 @@
 #include <delay.h>
 #include <rules.h>
 
-void *cbmem_top(void)
-{
-	return NULL;
-}
-
 void southbridge_smi_set_eos(void)
 {
 }