diff --git a/src/soc/intel/tigerlake/acpi/tcss.asl b/src/soc/intel/tigerlake/acpi/tcss.asl
index 50307f4db7..0606d20a01 100644
--- a/src/soc/intel/tigerlake/acpi/tcss.asl
+++ b/src/soc/intel/tigerlake/acpi/tcss.asl
@@ -1,6 +1,7 @@
 /* SPDX-License-Identifier: GPL-2.0-or-later */
 
 #include <soc/iomap.h>
+#include <soc/tcss.h>
 
 /*
  * Type C Subsystem(TCSS) topology provides Runtime D3 support for USB host controller(xHCI),
diff --git a/src/soc/intel/tigerlake/acpi/tcss_pcierp.asl b/src/soc/intel/tigerlake/acpi/tcss_pcierp.asl
index 2d40dc31e4..5ef5dff503 100644
--- a/src/soc/intel/tigerlake/acpi/tcss_pcierp.asl
+++ b/src/soc/intel/tigerlake/acpi/tcss_pcierp.asl
@@ -1,25 +1,5 @@
 /* SPDX-License-Identifier: GPL-2.0-or-later */
 
-/*
- * The PCI-SIG engineering change requirement provides the ACPI additions for firmware latency
- * optimization. Both of FW_RESET_TIME and FW_D3HOT_TO_D0_TIME are applicable to the upstream
- * port of the USB4/TBT topology.
- */
-/* Number of microseconds to wait after a conventional reset */
-#define FW_RESET_TIME			50000
-
-/* Number of microseconds to wait after data link layer active report */
-#define FW_DL_UP_TIME			1
-
-/* Number of microseconds to wait after a function level reset */
-#define FW_FLR_RESET_TIME		1
-
-/* Number of microseconds to wait from D3 hot to D0 transition */
-#define FW_D3HOT_TO_D0_TIME		50000
-
-/* Number of microseconds to wait after setting the VF enable bit  */
-#define FW_VF_ENABLE_TIME		1
-
 OperationRegion (PXCS, SystemMemory, BASE(_ADR), 0x800)
 Field (PXCS, AnyAcc, NoLock, Preserve)
 {
diff --git a/src/soc/intel/tigerlake/include/soc/tcss.h b/src/soc/intel/tigerlake/include/soc/tcss.h
index 014e3076e6..05baf5d534 100644
--- a/src/soc/intel/tigerlake/include/soc/tcss.h
+++ b/src/soc/intel/tigerlake/include/soc/tcss.h
@@ -13,4 +13,24 @@
 #define IOM_AUX_BIAS_CTRL_PULLDOWN_OFFSET_0	0x1088
 #define IOM_AUX_BIAS_CTRL_PULLDOWN_OFFSET(x)	(IOM_AUX_BIAS_CTRL_PULLDOWN_OFFSET_0 + (x) * 4)
 
+/*
+ * The PCI-SIG engineering change requirement provides the ACPI additions for firmware latency
+ * optimization. Both of FW_RESET_TIME and FW_D3HOT_TO_D0_TIME are applicable to the upstream
+ * port of the USB4/TBT topology.
+ */
+/* Number of microseconds to wait after a conventional reset */
+#define FW_RESET_TIME			50000
+
+/* Number of microseconds to wait after data link layer active report */
+#define FW_DL_UP_TIME			1
+
+/* Number of microseconds to wait after a function level reset */
+#define FW_FLR_RESET_TIME		1
+
+/* Number of microseconds to wait from D3 hot to D0 transition */
+#define FW_D3HOT_TO_D0_TIME		50000
+
+/* Number of microseconds to wait after setting the VF enable bit  */
+#define FW_VF_ENABLE_TIME		1
+
 #endif /* _SOC_TCSS_H_ */