mb/intel/jasperlake_rvp: do UART pad config at board-level

UART pad configuration should not be done in common code, because that
may cause short circuits, when the user sets a wrong UART index. Thus,
add the corresponding pads to the early UART gpio table for the board as
a first step. Common UART pad config code then gets dropped in CB:48829.

Also switch to `bootblock_mainboard_early_init` to configure the pads in
early bootblock before console initialization, to make the console work
as early as possible. The board does not do any other gpio configuration
in bootblock, so this should not influence behaviour in a negative way
(e.g. breaking overrides).

Change-Id: Ie3878b47b8e20c51b928a38df9ccedf2d50d478e
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49431
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

src/mainboard/intel/jasperlake_rvp/bootblock.c

@@ -5,7 +5,7 @@
 #include <bootblock_common.h>
 #include <soc/gpio.h>
 
-void bootblock_mainboard_init(void)
+void bootblock_mainboard_early_init(void)
 {
 	const struct pad_config *pads;
 	size_t num;

src/mainboard/intel/jasperlake_rvp/variants/jslrvp/gpio.c

@@ -310,6 +310,13 @@ static const struct pad_config gpio_table[] = {
 
 /* Early pad configuration in bootblock */
 static const struct pad_config early_gpio_table[] = {
+#if CONFIG(BOARD_INTEL_JASPERLAKE_RVP_EXT_EC)
+	/* UART2 RX */
+	PAD_CFG_NF(GPP_C20, NONE, DEEP, NF1),
+
+	/* UART2 TX */
+	PAD_CFG_NF(GPP_C21, NONE, DEEP, NF1),
+#endif
 
 	/* GSPI1_CS# */
 	PAD_CFG_NF(GPP_B19, NONE, DEEP, NF1),