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Add support for Google's Chromebook Pixel 

Ladies and gentlemen, I'm very happy to announce coreboot support for
the latest and greatest Google Chromebook: The Chromebook Pixel.

See the link below for more information on the Chromebook Pixel, and
its exciting specs:
http://www.google.com/intl/en/chrome/devices/chromebooks.html#pixel

The device is running coreboot and open source firmware on the EC
(see ChromeEC commit for more information on that exciting topic)

Change-Id: I03d00cf391bbb1a32f330793fe9058493e088571
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/2482
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
This commit is contained in:
Stefan Reinauer 2013-02-21 15:48:37 -08:00 committed by Ronald G. Minnich
parent 940095fe5e
commit 49428d8403
34 changed files with 8060 additions and 1 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

4
src/mainboard/google/Kconfig
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@ -25,12 +25,14 @@ config BOARD_GOOGLE_BUTTERFLY
bool "Butterfly" bool "Butterfly"
config BOARD_GOOGLE_PARROT config BOARD_GOOGLE_PARROT
bool "Parrot" bool "Parrot"
config BOARD_GOOGLE_LINK
bool "Link"
config BOARD_GOOGLE_SNOW config BOARD_GOOGLE_SNOW
bool "Snow" bool "Snow"
endchoice endchoice
source "src/mainboard/google/butterfly/Kconfig" source "src/mainboard/google/butterfly/Kconfig"
source "src/mainboard/google/link/Kconfig"
source "src/mainboard/google/parrot/Kconfig" source "src/mainboard/google/parrot/Kconfig"
source "src/mainboard/google/snow/Kconfig" source "src/mainboard/google/snow/Kconfig"

48
src/mainboard/google/link/Kconfig Normal file
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@ -0,0 +1,48 @@
if BOARD_GOOGLE_LINK
config BOARD_SPECIFIC_OPTIONS # dummy
def_bool y
select ARCH_X86
select CPU_INTEL_SOCKET_RPGA989
select NORTHBRIDGE_INTEL_IVYBRIDGE
select SOUTHBRIDGE_INTEL_C216
select BOARD_ROMSIZE_KB_8192
select EC_GOOGLE_CHROMEEC
select BOARD_HAS_FADT
select HAVE_ACPI_TABLES
select HAVE_OPTION_TABLE
select HAVE_ACPI_RESUME
select HAVE_MAINBOARD_RESOURCES
select MMCONF_SUPPORT
select HAVE_SMI_HANDLER
select GFXUMA
select CHROMEOS
select EXTERNAL_MRC_BLOB
select SERIRQ_CONTINUOUS_MODE
select MAINBOARD_HAS_NATIVE_VGA_INIT
config MAINBOARD_DIR
string
default google/link
config MAINBOARD_PART_NUMBER
string
default "Link"
config MMCONF_BASE_ADDRESS
hex
default 0xf0000000
config IRQ_SLOT_COUNT
int
default 18
config MAX_CPUS
int
default 8
config VGA_BIOS_FILE
string
default "pci8086,0166.rom"
endif # BOARD_GOOGLE_LINK

46
src/mainboard/google/link/Makefile.inc Normal file
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@ -0,0 +1,46 @@
##
## This file is part of the coreboot project.
##
## Copyright (C) 2011 Google Inc.
##
## This program is free software; you can redistribute it and/or modify
## it under the terms of the GNU General Public License as published by
## the Free Software Foundation; version 2 of the License.
##
## This program is distributed in the hope that it will be useful,
## but WITHOUT ANY WARRANTY; without even the implied warranty of
## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
## GNU General Public License for more details.
##
## You should have received a copy of the GNU General Public License
## along with this program; if not, write to the Free Software
## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
##
ramstage-y += ec.c
romstage-$(CONFIG_CHROMEOS) += chromeos.c
ramstage-$(CONFIG_CHROMEOS) += chromeos.c
ramstage-$(CONFIG_MAINBOARD_DO_NATIVE_VGA_INIT) += i915.c
ramstage-$(CONFIG_MAINBOARD_DO_NATIVE_VGA_INIT) += i915io.c
smm-$(CONFIG_HAVE_SMI_HANDLER) += mainboard_smi.c
SPD_BIN = $(obj)/spd.bin
SRC_ROOT = $(src)/mainboard/google/link
# Order of names in SPD_SOURCES is important!
SPD_SOURCES = elpida_4Gb_1600_x16
SPD_SOURCES += samsung_4Gb_1600_1.35v_x16
SPD_SOURCES += micron_4Gb_1600_1.35v_x16
SPD_DEPS := $(foreach f, $(SPD_SOURCES), $(SRC_ROOT)/$(f).spd.hex)
# Include spd rom data
$(SPD_BIN): $(SPD_DEPS)
for f in $^; do for c in $$(cat $$f); do echo -e -n "\\x$$c"; done; done > $@
cbfs-files-y += spd.bin
spd.bin-file := $(SPD_BIN)
spd.bin-type := 0xab
spd.bin-position := 0xfffec000

23
src/mainboard/google/link/acpi/chromeos.asl Normal file
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@ -0,0 +1,23 @@
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2011 Google Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
Name(OIPG, Package() {
Package() { 0x001, 0, 9, "PantherPoint" }, // recovery button
Package() { 0x003, 1, 57, "PantherPoint" }, // firmware write protect
})

24
src/mainboard/google/link/acpi/ec.asl Normal file
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@ -0,0 +1,24 @@
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2012 Google Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
/* mainboard configuration */
#include "../ec.h"
/* ACPI code for EC functions */
#include "../../../../ec/google/chromeec/acpi/ec.asl"

69
src/mainboard/google/link/acpi/ivybridge_pci_irqs.asl Normal file
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@ -0,0 +1,69 @@
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2007-2009 coresystems GmbH
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
/* This is board specific information: IRQ routing for IvyBridge */
// PCI Interrupt Routing
Method(_PRT)
{
If (PICM) {
Return (Package() {
// Onboard graphics (IGD) 0:2.0
Package() { 0x0002ffff, 0, 0, 16 },
// High Definition Audio 0:1b.0
Package() { 0x001bffff, 0, 0, 22 },
// PCIe Root Ports 0:1c.x
Package() { 0x001cffff, 0, 0, 19 },
Package() { 0x001cffff, 1, 0, 20 },
Package() { 0x001cffff, 2, 0, 17 },
Package() { 0x001cffff, 3, 0, 18 },
// EHCI #1 0:1d.0
Package() { 0x001dffff, 0, 0, 19 },
// EHCI #2 0:1a.0
Package() { 0x001affff, 0, 0, 20 },
// LPC devices 0:1f.0
Package() { 0x001fffff, 0, 0, 21 },
Package() { 0x001fffff, 1, 0, 22 },
Package() { 0x001fffff, 2, 0, 23 },
Package() { 0x001fffff, 3, 0, 16 },
})
} Else {
Return (Package() {
// Onboard graphics (IGD) 0:2.0
Package() { 0x0002ffff, 0, \_SB.PCI0.LPCB.LNKA, 0 },
// High Definition Audio 0:1b.0
Package() { 0x001bffff, 0, \_SB.PCI0.LPCB.LNKG, 0 },
// PCIe Root Ports 0:1c.x
Package() { 0x001cffff, 0, \_SB.PCI0.LPCB.LNKD, 0 },
Package() { 0x001cffff, 1, \_SB.PCI0.LPCB.LNKE, 0 },
Package() { 0x001cffff, 2, \_SB.PCI0.LPCB.LNKB, 0 },
Package() { 0x001cffff, 3, \_SB.PCI0.LPCB.LNKC, 0 },
// EHCI #1 0:1d.0
Package() { 0x001dffff, 0, \_SB.PCI0.LPCB.LNKD, 0 },
// EHCI #2 0:1a.0
Package() { 0x001affff, 0, \_SB.PCI0.LPCB.LNKE, 0 },
// LPC device 0:1f.0
Package() { 0x001fffff, 0, \_SB.PCI0.LPCB.LNKF, 0 },
Package() { 0x001fffff, 1, \_SB.PCI0.LPCB.LNKG, 0 },
Package() { 0x001fffff, 2, \_SB.PCI0.LPCB.LNKH, 0 },
Package() { 0x001fffff, 3, \_SB.PCI0.LPCB.LNKA, 0 },
})
}
}

103
src/mainboard/google/link/acpi/mainboard.asl Normal file
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@ -0,0 +1,103 @@
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2011 Google Inc.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; version 2 of
* the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
* MA 02110-1301 USA
*/
Scope (\_SB) {
Device (LID0)
{
Name(_HID, EisaId("PNP0C0D"))
Method(_LID, 0)
{
Store (\_SB.PCI0.LPCB.EC0.LIDS, \LIDS)
Return (\LIDS)
}
// EC_LID_OUT is GPIO15
Name(_PRW, Package(){0x1f, 0x05})
}
Device (PWRB)
{
Name(_HID, EisaId("PNP0C0C"))
}
Device (TPAD)
{
Name (_ADR, 0x0)
Name (_UID, 1)
// Report as a Sleep Button device so Linux will
// automatically enable it as a wake source
Name(_HID, EisaId("PNP0C0E"))
// Trackpad Wake is GPIO12
Name(_PRW, Package(){0x1c, 0x03})
Name(_CRS, ResourceTemplate()
{
// PIRQE -> GSI20
Interrupt (ResourceConsumer, Edge, ActiveLow) {20}
// SMBUS Address 0x4b
VendorShort (ADDR) {0x4b}
})
}
Device (TSCR)
{
Name (_ADR, 0x0)
Name (_UID, 2)
// Report as a Sleep Button device so Linux will
// automatically enable it as a wake source
Name(_HID, EisaId("PNP0C0E"))
// Touchscreen Wake is GPIO14
Name(_PRW, Package(){0x1e, 0x03})
Name(_CRS, ResourceTemplate()
{
// PIRQG -> GSI22
Interrupt (ResourceConsumer, Edge, ActiveLow) {22}
// SMBUS Address 0x4a
VendorShort (ADDR) {0x4a}
})
}
// Keyboard Backlight interface via EC
Device (KBLT) {
Name (_HID, EisaId("GGL0002"))
Name (_UID, 1)
Name (_ADR, 0)
// Read current backlight value
Method (KBQC, 0)
{
Return (\_SB.PCI0.LPCB.EC0.KBLV)
}
// Write new backlight value
Method (KBCM, 1)
{
Store (Arg0, \_SB.PCI0.LPCB.EC0.KBLV)
}
}
}

88
src/mainboard/google/link/acpi/platform.asl Normal file
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@ -0,0 +1,88 @@
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2012 Google Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
/* The APM port can be used for generating software SMIs */
OperationRegion (APMP, SystemIO, 0xb2, 2)
Field (APMP, ByteAcc, NoLock, Preserve)
{
APMC, 8, // APM command
APMS, 8 // APM status
}
/* Port 80 POST */
OperationRegion (POST, SystemIO, 0x80, 1)
Field (POST, ByteAcc, Lock, Preserve)
{
DBG0, 8
}
/* SMI I/O Trap */
Method(TRAP, 1, Serialized)
{
Store (Arg0, SMIF) // SMI Function
Store (0, TRP0) // Generate trap
Return (SMIF) // Return value of SMI handler
}
/* The _PIC method is called by the OS to choose between interrupt
* routing via the i8259 interrupt controller or the APIC.
*
* _PIC is called with a parameter of 0 for i8259 configuration and
* with a parameter of 1 for Local Apic/IOAPIC configuration.
*/
Method(_PIC, 1)
{
// Remember the OS' IRQ routing choice.
Store(Arg0, PICM)
}
/* The _PTS method (Prepare To Sleep) is called before the OS is
* entering a sleep state. The sleep state number is passed in Arg0
*/
Method(_PTS,1)
{
/* Disable WWAN */
Store (Zero, GP36)
}
/* The _WAK method is called on system wakeup */
Method(_WAK,1)
{
/* Update AC status */
Store (\_SB.PCI0.LPCB.EC0.ACEX, Local0)
if (LNotEqual (Local0, \PWRS)) {
Store (Local0, \PWRS)
Notify (\_SB.PCI0.LPCB.EC0.AC, 0x80)
}
/* Update LID status */
Store (\_SB.PCI0.LPCB.EC0.LIDS, Local0)
if (LNotEqual (Local0, \LIDS)) {
Store (Local0, \LIDS)
Notify (\_SB.LID0, 0x80)
}
Return(Package(){0,0})
}

69
src/mainboard/google/link/acpi/sandybridge_pci_irqs.asl Normal file
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@ -0,0 +1,69 @@
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2007-2009 coresystems GmbH
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
/* This is board specific information: IRQ routing for Sandybridge */
// PCI Interrupt Routing
Method(_PRT)
{
If (PICM) {
Return (Package() {
// Onboard graphics (IGD) 0:2.0
Package() { 0x0002ffff, 0, 0, 16 },
// High Definition Audio 0:1b.0
Package() { 0x001bffff, 0, 0, 16 },
// PCIe Root Ports 0:1c.x
Package() { 0x001cffff, 0, 0, 19 },
Package() { 0x001cffff, 1, 0, 20 },
Package() { 0x001cffff, 2, 0, 17 },
Package() { 0x001cffff, 3, 0, 18 },
// EHCI #1 0:1d.0
Package() { 0x001dffff, 0, 0, 19 },
// EHCI #2 0:1a.0
Package() { 0x001affff, 0, 0, 21 },
// LPC devices 0:1f.0
Package() { 0x001fffff, 0, 0, 17 },
Package() { 0x001fffff, 1, 0, 23 },
Package() { 0x001fffff, 2, 0, 16 },
Package() { 0x001fffff, 3, 0, 18 },
})
} Else {
Return (Package() {
// Onboard graphics (IGD) 0:2.0
Package() { 0x0002ffff, 0, \_SB.PCI0.LPCB.LNKA, 0 },
// High Definition Audio 0:1b.0
Package() { 0x001bffff, 0, \_SB.PCI0.LPCB.LNKA, 0 },
// PCIe Root Ports 0:1c.x
Package() { 0x001cffff, 0, \_SB.PCI0.LPCB.LNKD, 0 },
Package() { 0x001cffff, 1, \_SB.PCI0.LPCB.LNKE, 0 },
Package() { 0x001cffff, 2, \_SB.PCI0.LPCB.LNKB, 0 },
Package() { 0x001cffff, 3, \_SB.PCI0.LPCB.LNKC, 0 },
// EHCI #1 0:1d.0
Package() { 0x001dffff, 0, \_SB.PCI0.LPCB.LNKD, 0 },
// EHCI #2 0:1a.0
Package() { 0x001affff, 0, \_SB.PCI0.LPCB.LNKF, 0 },
// LPC device 0:1f.0
Package() { 0x001fffff, 0, \_SB.PCI0.LPCB.LNKB, 0 },
Package() { 0x001fffff, 1, \_SB.PCI0.LPCB.LNKH, 0 },
Package() { 0x001fffff, 2, \_SB.PCI0.LPCB.LNKA, 0 },
Package() { 0x001fffff, 3, \_SB.PCI0.LPCB.LNKC, 0 },
})
}
}

29
src/mainboard/google/link/acpi/superio.asl Normal file
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@ -0,0 +1,29 @@
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2012 Google Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
/* mainboard configuration */
#include "../ec.h"
#define SIO_EC_MEMMAP_ENABLE // EC Memory Map Resources
#define SIO_EC_HOST_ENABLE // EC Host Interface Resources
#define SIO_EC_ENABLE_PS2K // Enable PS/2 Keyboard
#define SIO_EC_ENABLE_COM1 // Enable Serial Port 1
/* ACPI code for EC SuperIO functions */
#include "../../../../ec/google/chromeec/acpi/superio.asl"

219
src/mainboard/google/link/acpi/thermal.asl Normal file
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@ -0,0 +1,219 @@
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2011 Google Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
// Thermal Zone
Scope (\_TZ)
{
ThermalZone (CRIT)
{
// Thermal zone polling frequency: 5 seconds
Name (_TZP, 50)
// Convert from Degrees C to 1/10 Kelvin for ACPI
Method (CTOK, 1) {
// 10th of Degrees C
Multiply (Arg0, 10, Local0)
// Convert to Kelvin
Add (Local0, 2732, Local0)
Return (Local0)
}
// Threshold for OS to shutdown
Method (_CRT, 0, Serialized)
{
Return (CTOK (\TCRT))
}
Method (_TMP, 0, Serialized)
{
// Get CPU Temperature from TIN9/PECI via EC
Store (\_SB.PCI0.LPCB.EC0.TIN9, Local0)
// Check for sensor not present
If (LEqual (Local0, \_SB.PCI0.LPCB.EC0.TNPR)) {
Return (CTOK(0))
}
// Check for sensor not powered
If (LEqual (Local0, \_SB.PCI0.LPCB.EC0.TNOP)) {
Return (CTOK(0))
}
// Check for sensor bad reading
If (LEqual (Local0, \_SB.PCI0.LPCB.EC0.TBAD)) {
Return (CTOK(0))
}
// Adjust by offset to get Kelvin
Add (\_SB.PCI0.LPCB.EC0.TOFS, Local0, Local0)
// Convert to 1/10 Kelvin
Multiply (Local0, 10, Local0)
Return (Local0)
}
}
ThermalZone (THRM)
{
Name (_TC1, 0x02)
Name (_TC2, 0x05)
// Thermal zone polling frequency: 10 seconds
Name (_TZP, 100)
// Thermal sampling period for passive cooling: 2 seconds
Name (_TSP, 20)
// Convert from Degrees C to 1/10 Kelvin for ACPI
Method (CTOK, 1) {
// 10th of Degrees C
Multiply (Arg0, 10, Local0)
// Convert to Kelvin
Add (Local0, 2732, Local0)
Return (Local0)
}
// Threshold for OS to shutdown
Method (_CRT, 0, Serialized)
{
Return (CTOK (\TCRT))
}
// Threshold for passive cooling
Method (_PSV, 0, Serialized)
{
Return (CTOK (\TPSV))
}
// Processors used for passive cooling
Method (_PSL, 0, Serialized)
{
Return (\PPKG ())
}
Method (_TMP, 0, Serialized)
{
// Get Temperature from TIN# set in NVS
Store (\_SB.PCI0.LPCB.EC0.TINS (TMPS), Local0)
// Check for sensor not present
If (LEqual (Local0, \_SB.PCI0.LPCB.EC0.TNPR)) {
Return (CTOK(0))
}
// Check for sensor not powered
If (LEqual (Local0, \_SB.PCI0.LPCB.EC0.TNOP)) {
Return (CTOK(0))
}
// Check for sensor bad reading
If (LEqual (Local0, \_SB.PCI0.LPCB.EC0.TBAD)) {
Return (CTOK(0))
}
// Adjust by offset to get Kelvin
Add (\_SB.PCI0.LPCB.EC0.TOFS, Local0, Local0)
// Convert to 1/10 Kelvin
Multiply (Local0, 10, Local0)
Return (Local0)
}
/* CTDP Down */
Method (_AC0) {
If (LLessEqual (\FLVL, 0)) {
Return (CTOK (\F0OF))
} Else {
Return (CTOK (\F0ON))
}
}
/* CTDP Nominal */
Method (_AC1) {
If (LLessEqual (\FLVL, 1)) {
Return (CTOK (\F1OF))
} Else {
Return (CTOK (\F1ON))
}
}
Name (_AL0, Package () { TDP0 })
Name (_AL1, Package () { TDP1 })
PowerResource (TNP0, 0, 0)
{
Method (_STA) {
If (LLessEqual (\FLVL, 0)) {
Return (One)
} Else {
Return (Zero)
}
}
Method (_ON) {
Store (0, \FLVL)
\_SB.PCI0.MCHC.STND ()
Notify (\_TZ.THRM, 0x81)
}
Method (_OFF) {
Store (1, \FLVL)
\_SB.PCI0.MCHC.STDN ()
Notify (\_TZ.THRM, 0x81)
}
}
PowerResource (TNP1, 0, 0)
{
Method (_STA) {
If (LLessEqual (\FLVL, 1)) {
Return (One)
} Else {
Return (Zero)
}
}
Method (_ON) {
Store (1, \FLVL)
Notify (\_TZ.THRM, 0x81)
}
Method (_OFF) {
Store (1, \FLVL)
Notify (\_TZ.THRM, 0x81)
}
}
Device (TDP0)
{
Name (_HID, EISAID ("PNP0C0B"))
Name (_UID, 0)
Name (_PR0, Package () { TNP0 })
}
Device (TDP1)
{
Name (_HID, EISAID ("PNP0C0B"))
Name (_UID, 1)
Name (_PR0, Package () { TNP1 })
}
}
}

43
src/mainboard/google/link/acpi/video.asl Normal file
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/*
* This file is part of the coreboot project.
*
* Copyright (C) 2007-2009 coresystems GmbH
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
// Brightness write
Method (BRTW, 1, Serialized)
{
// TODO
}
// Hot Key Display Switch
Method (HKDS, 1, Serialized)
{
// TODO
}
// Lid Switch Display Switch
Method (LSDS, 1, Serialized)
{
// TODO
}
// Brightness Notification
Method(BRTN,1,Serialized)
{
// TODO (no displays defined yet)
}

288
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/*
* This file is part of the coreboot project.
*
* Copyright (C) 2007-2009 coresystems GmbH
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
#include <types.h>
#include <string.h>
#include <cbmem.h>
#include <console/console.h>
#include <arch/acpi.h>
#include <arch/ioapic.h>
#include <arch/acpigen.h>
#include <arch/smp/mpspec.h>
#include <device/device.h>
#include <device/pci.h>
#include <device/pci_ids.h>
#include <cpu/cpu.h>
#include <cpu/x86/msr.h>
#include <vendorcode/google/chromeos/gnvs.h>
#include <ec/google/chromeec/ec.h>
extern const unsigned char AmlCode[];
#if CONFIG_HAVE_ACPI_SLIC
unsigned long acpi_create_slic(unsigned long current);
#endif
#include <northbridge/intel/sandybridge/sandybridge.h>
#include <southbridge/intel/bd82x6x/pch.h>
#include <southbridge/intel/bd82x6x/nvs.h>
#include "thermal.h"
static void acpi_update_thermal_table(global_nvs_t *gnvs)
{
gnvs->tmps = CTDP_SENSOR_ID;
gnvs->f1of = CTDP_NOMINAL_THRESHOLD_OFF;
gnvs->f1on = CTDP_NOMINAL_THRESHOLD_ON;
gnvs->f0of = CTDP_DOWN_THRESHOLD_OFF;
gnvs->f0on = CTDP_DOWN_THRESHOLD_ON;
gnvs->tcrt = CRITICAL_TEMPERATURE;
gnvs->tpsv = PASSIVE_TEMPERATURE;
gnvs->tmax = MAX_TEMPERATURE;
gnvs->flvl = 1;
}
static void acpi_create_gnvs(global_nvs_t *gnvs, igd_opregion_t *opregion)
{
memset((void *)gnvs, 0, sizeof(*gnvs));
gnvs->apic = 1;
gnvs->mpen = 1; /* Enable Multi Processing */
gnvs->pcnt = dev_count_cpu();
/* Disable USB ports in S3 by default */
gnvs->s3u0 = 0;
gnvs->s3u1 = 0;
/* Disable USB ports in S5 by default */
gnvs->s5u0 = 0;
gnvs->s5u1 = 0;
/* CBMEM TOC */
gnvs->cmem = (u32)get_cbmem_toc();
/* IGD Displays */
gnvs->ndid = 1;
gnvs->did[0] = 0x80000000;
gnvs->did[1] = 0x80000000;
gnvs->did[2] = 0x00000000;
gnvs->did[3] = 0x00000000;
gnvs->did[4] = 0x00000000;
#if CONFIG_CHROMEOS
// TODO(reinauer) this could move elsewhere?
chromeos_init_vboot(&(gnvs->chromeos));
gnvs->chromeos.vbt2 = google_ec_running_ro() ?
ACTIVE_ECFW_RO : ACTIVE_ECFW_RW;
#endif
/* IGD OpRegion Base Address */
gnvs->aslb = (u32)opregion;
acpi_update_thermal_table(gnvs);
// the lid is open by default.
gnvs->lids = 1;
}
unsigned long acpi_fill_madt(unsigned long current)
{
/* Local APICs */
current = acpi_create_madt_lapics(current);
/* IOAPIC */
current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current,
2, IO_APIC_ADDR, 0);
/* INT_SRC_OVR */
current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *)
current, 0, 0, 2, 0);
current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *)
current, 0, 9, 9, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_HIGH);
return current;
}
unsigned long acpi_fill_ssdt_generator(unsigned long current,
const char *oem_table_id)
{
generate_cpu_entries();
return (unsigned long) (acpigen_get_current());
}
unsigned long acpi_fill_slit(unsigned long current)
{
// Not implemented
return current;
}
unsigned long acpi_fill_srat(unsigned long current)
{
/* No NUMA, no SRAT */
return current;
}
#define ALIGN_CURRENT current = (ALIGN(current, 16))
unsigned long write_acpi_tables(unsigned long start)
{
unsigned long current;
int i;
acpi_rsdp_t *rsdp;
acpi_rsdt_t *rsdt;
acpi_xsdt_t *xsdt;
acpi_hpet_t *hpet;
acpi_madt_t *madt;
acpi_mcfg_t *mcfg;
acpi_fadt_t *fadt;
acpi_facs_t *facs;
#if CONFIG_HAVE_ACPI_SLIC
acpi_header_t *slic;
#endif
acpi_header_t *ssdt;
acpi_header_t *dsdt;
igd_opregion_t *opregion;
current = start;
/* Align ACPI tables to 16byte */
ALIGN_CURRENT;
printk(BIOS_INFO, "ACPI: Writing ACPI tables at %lx.\n", start);
/* We need at least an RSDP and an RSDT Table */
rsdp = (acpi_rsdp_t *) current;
current += sizeof(acpi_rsdp_t);
ALIGN_CURRENT;
rsdt = (acpi_rsdt_t *) current;
current += sizeof(acpi_rsdt_t);
ALIGN_CURRENT;
xsdt = (acpi_xsdt_t *) current;
current += sizeof(acpi_xsdt_t);
ALIGN_CURRENT;
/* clear all table memory */
memset((void *) start, 0, current - start);
acpi_write_rsdp(rsdp, rsdt, xsdt);
acpi_write_rsdt(rsdt);
acpi_write_xsdt(xsdt);
printk(BIOS_DEBUG, "ACPI: * FACS\n");
facs = (acpi_facs_t *) current;
current += sizeof(acpi_facs_t);
ALIGN_CURRENT;
acpi_create_facs(facs);
printk(BIOS_DEBUG, "ACPI: * DSDT\n");
dsdt = (acpi_header_t *) current;
memcpy(dsdt, &AmlCode, sizeof(acpi_header_t));
current += dsdt->length;
memcpy(dsdt, &AmlCode, dsdt->length);
ALIGN_CURRENT;
printk(BIOS_DEBUG, "ACPI: * FADT\n");
fadt = (acpi_fadt_t *) current;
current += sizeof(acpi_fadt_t);
ALIGN_CURRENT;
acpi_create_fadt(fadt, facs, dsdt);
acpi_add_table(rsdp, fadt);
/*
* We explicitly add these tables later on:
*/
printk(BIOS_DEBUG, "ACPI: * HPET\n");
hpet = (acpi_hpet_t *) current;
current += sizeof(acpi_hpet_t);
ALIGN_CURRENT;
acpi_create_hpet(hpet);
acpi_add_table(rsdp, hpet);
/* If we want to use HPET Timers Linux wants an MADT */
printk(BIOS_DEBUG, "ACPI: * MADT\n");
madt = (acpi_madt_t *) current;
acpi_create_madt(madt);
current += madt->header.length;
ALIGN_CURRENT;
acpi_add_table(rsdp, madt);
printk(BIOS_DEBUG, "ACPI: * MCFG\n");
mcfg = (acpi_mcfg_t *) current;
acpi_create_mcfg(mcfg);
current += mcfg->header.length;
ALIGN_CURRENT;
acpi_add_table(rsdp, mcfg);
printk(BIOS_DEBUG, "ACPI: * IGD OpRegion\n");
opregion = (igd_opregion_t *)current;
init_igd_opregion(opregion);
current += sizeof(igd_opregion_t);
ALIGN_CURRENT;
printk(BIOS_DEBUG, "ACPI: * GNVS\n");
/* Pack GNVS into the ACPI table area */
for (i=0; i < dsdt->length; i++) {
if (*(u32*)(((u32)dsdt) + i) == 0xC0DEBABE) {
printk(BIOS_DEBUG, "ACPI: Patching up global NVS in "
"DSDT at offset 0x%04x -> 0x%08lx\n", i, current);
*(u32*)(((u32)dsdt) + i) = current; // 0x92 bytes
acpi_save_gnvs(current);
break;
}
}
/* And fill it */
acpi_create_gnvs((global_nvs_t *)current, opregion);
/* And tell SMI about it */
smm_setup_structures((void *)current, NULL, NULL);
current += sizeof(global_nvs_t);
ALIGN_CURRENT;
/* We patched up the DSDT, so we need to recalculate the checksum */
dsdt->checksum = 0;
dsdt->checksum = acpi_checksum((void *)dsdt, dsdt->length);
printk(BIOS_DEBUG, "ACPI: * DSDT @ %p Length %x\n", dsdt,
dsdt->length);
#if CONFIG_HAVE_ACPI_SLIC
printk(BIOS_DEBUG, "ACPI: * SLIC\n");
slic = (acpi_header_t *)current;
current += acpi_create_slic(current);
ALIGN_CURRENT;
acpi_add_table(rsdp, slic);
#endif
printk(BIOS_DEBUG, "ACPI: * SSDT\n");
ssdt = (acpi_header_t *)current;
acpi_create_ssdt_generator(ssdt, ACPI_TABLE_CREATOR);
current += ssdt->length;
acpi_add_table(rsdp, ssdt);
ALIGN_CURRENT;
printk(BIOS_DEBUG, "current = %lx\n", current);
printk(BIOS_INFO, "ACPI: done.\n");
return current;
}

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/*
* This file is part of the coreboot project.
*
* Copyright (C) 2011 Google Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
#include <string.h>
#include <vendorcode/google/chromeos/chromeos.h>
#include <arch/io.h>
#ifdef __PRE_RAM__
#include <arch/romcc_io.h>
#else
#include <device/device.h>
#include <device/pci.h>
#endif
#include <southbridge/intel/bd82x6x/pch.h>
#include "ec.h"
#include <ec/google/chromeec/ec.h>
#ifndef __PRE_RAM__
#include <boot/coreboot_tables.h>
#include <arch/coreboot_tables.h>
#define GPIO_COUNT 6
#define ACTIVE_LOW 0
#define ACTIVE_HIGH 1
static int get_lid_switch(void)
{
u8 ec_switches = inb(EC_LPC_ADDR_MEMMAP + EC_MEMMAP_SWITCHES);
return !!(ec_switches & EC_SWITCH_LID_OPEN);
}
void fill_lb_gpios(struct lb_gpios *gpios)
{
device_t dev = dev_find_slot(0, PCI_DEVFN(0x1f,0));
u16 gpio_base = pci_read_config32(dev, GPIOBASE) & 0xfffe;
//u16 gen_pmcon_1 = pci_read_config32(dev, GEN_PMCON_1);
if (!gpio_base)
return;
u32 gp_lvl2 = inl(gpio_base + 0x38);
gpios->size = sizeof(*gpios) + (GPIO_COUNT * sizeof(struct lb_gpio));
gpios->count = GPIO_COUNT;
/* Write Protect: GPIO57 = PCH_SPI_WP_D */
gpios->gpios[0].port = 57;
gpios->gpios[0].polarity = ACTIVE_HIGH;
gpios->gpios[0].value = (gp_lvl2 >> (57 - 32)) & 1;
strncpy((char *)gpios->gpios[0].name,"write protect",
GPIO_MAX_NAME_LENGTH);
/* Recovery: the "switch" comes from the EC */
gpios->gpios[1].port = -1; /* Indicate that this is a pseudo GPIO */
gpios->gpios[1].polarity = ACTIVE_HIGH;
gpios->gpios[1].value = get_recovery_mode_switch();
strncpy((char *)gpios->gpios[1].name,"recovery", GPIO_MAX_NAME_LENGTH);
/* Lid: the "switch" comes from the EC */
gpios->gpios[2].port = -1;
gpios->gpios[2].polarity = ACTIVE_HIGH;
gpios->gpios[2].value = get_lid_switch();
strncpy((char *)gpios->gpios[2].name,"lid", GPIO_MAX_NAME_LENGTH);
/* Power Button: hard-coded as not pressed; we'll detect later presses
* via SMI. */
gpios->gpios[3].port = -1;
gpios->gpios[3].polarity = ACTIVE_HIGH;
gpios->gpios[3].value = 0;
strncpy((char *)gpios->gpios[3].name,"power", GPIO_MAX_NAME_LENGTH);
/* Developer: a tricky case on Link, there is no switch */
gpios->gpios[4].port = -1; /* Indicate that this is a pseudo GPIO */
gpios->gpios[4].polarity = ACTIVE_HIGH;
gpios->gpios[4].value = get_developer_mode_switch();
strncpy((char *)gpios->gpios[4].name,"developer", GPIO_MAX_NAME_LENGTH);
/* Did we load the VGA Option ROM? */
gpios->gpios[5].port = -1; /* Indicate that this is a pseudo GPIO */
gpios->gpios[5].polarity = ACTIVE_HIGH;
gpios->gpios[5].value = oprom_is_loaded;
strncpy((char *)gpios->gpios[5].name,"oprom", GPIO_MAX_NAME_LENGTH);
}
#endif
/* The dev-switch is virtual on Link (and so handled elsewhere). */
int get_developer_mode_switch(void)
{
return 0;
}
/* There are actually two recovery switches. One is the magic keyboard chord,
* the other is driven by Servo. */
int get_recovery_mode_switch(void)
{
u8 ec_switches = inb(EC_LPC_ADDR_MEMMAP + EC_MEMMAP_SWITCHES);
u32 ec_events;
/* If a switch is set, we don't need to look at events. */
if (ec_switches & (EC_SWITCH_KEYBOARD_RECOVERY |
EC_SWITCH_DEDICATED_RECOVERY))
return 1;
/* Else check if the EC has posted the keyboard recovery event. */
ec_events = google_chromeec_get_events_b();
return !!(ec_events &
EC_HOST_EVENT_MASK(EC_HOST_EVENT_KEYBOARD_RECOVERY));
}

139
src/mainboard/google/link/cmos.layout Normal file
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##
## This file is part of the coreboot project.
##
## Copyright (C) 2007-2008 coresystems GmbH
##
## This program is free software; you can redistribute it and/or modify
## it under the terms of the GNU General Public License as published by
## the Free Software Foundation; version 2 of the License.
##
## This program is distributed in the hope that it will be useful,
## but WITHOUT ANY WARRANTY; without even the implied warranty of
## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
## GNU General Public License for more details.
##
## You should have received a copy of the GNU General Public License
## along with this program; if not, write to the Free Software
## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
##
# -----------------------------------------------------------------
entries
#start-bit length config config-ID name
#0 8 r 0 seconds
#8 8 r 0 alarm_seconds
#16 8 r 0 minutes
#24 8 r 0 alarm_minutes
#32 8 r 0 hours
#40 8 r 0 alarm_hours
#48 8 r 0 day_of_week
#56 8 r 0 day_of_month
#64 8 r 0 month
#72 8 r 0 year
# -----------------------------------------------------------------
# Status Register A
#80 4 r 0 rate_select
#84 3 r 0 REF_Clock
#87 1 r 0 UIP
# -----------------------------------------------------------------
# Status Register B
#88 1 r 0 auto_switch_DST
#89 1 r 0 24_hour_mode
#90 1 r 0 binary_values_enable
#91 1 r 0 square-wave_out_enable
#92 1 r 0 update_finished_enable
#93 1 r 0 alarm_interrupt_enable
#94 1 r 0 periodic_interrupt_enable
#95 1 r 0 disable_clock_updates
# -----------------------------------------------------------------
# Status Register C
#96 4 r 0 status_c_rsvd
#100 1 r 0 uf_flag
#101 1 r 0 af_flag
#102 1 r 0 pf_flag
#103 1 r 0 irqf_flag
# -----------------------------------------------------------------
# Status Register D
#104 7 r 0 status_d_rsvd
#111 1 r 0 valid_cmos_ram
# -----------------------------------------------------------------
# Diagnostic Status Register
#112 8 r 0 diag_rsvd1
# -----------------------------------------------------------------
0 120 r 0 reserved_memory
#120 264 r 0 unused
# -----------------------------------------------------------------
# RTC_BOOT_BYTE (coreboot hardcoded)
384 1 e 4 boot_option
385 1 e 4 last_boot
388 4 r 0 reboot_bits
#390 2 r 0 unused?
# -----------------------------------------------------------------
# coreboot config options: console
392 3 e 5 baud_rate
395 4 e 6 debug_level
#399 1 r 0 unused
# coreboot config options: cpu
400 1 e 2 hyper_threading
#401 7 r 0 unused
# coreboot config options: southbridge
408 1 e 1 nmi
409 2 e 7 power_on_after_fail
#411 5 r 0 unused
# coreboot config options: bootloader
#Used by ChromeOS:
416 128 r 0 vbnv
#544 440 r 0 unused
# SandyBridge MRC Scrambler Seed values
896 32 r 0 mrc_scrambler_seed
928 32 r 0 mrc_scrambler_seed_s3
# coreboot config options: check sums
984 16 h 0 check_sum
#1000 24 r 0 amd_reserved
# -----------------------------------------------------------------
enumerations
#ID value text
1 0 Disable
1 1 Enable
2 0 Enable
2 1 Disable
4 0 Fallback
4 1 Normal
5 0 115200
5 1 57600
5 2 38400
5 3 19200
5 4 9600
5 5 4800
5 6 2400
5 7 1200
6 1 Emergency
6 2 Alert
6 3 Critical
6 4 Error
6 5 Warning
6 6 Notice
6 7 Info
6 8 Debug
6 9 Spew
7 0 Disable
7 1 Enable
7 2 Keep
# -----------------------------------------------------------------
checksums
checksum 392 415 984

109
src/mainboard/google/link/devicetree.cb Normal file
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chip northbridge/intel/sandybridge
# Enable DisplayPort Hotplug with 6ms pulse
register "gpu_dp_d_hotplug" = "0x06"
# Enable Panel as eDP and configure power delays
register "gpu_panel_port_select" = "1" # eDP_A
register "gpu_panel_power_cycle_delay" = "6" # 500ms
register "gpu_panel_power_up_delay" = "2000" # 200ms
register "gpu_panel_power_down_delay" = "500" # 50ms
register "gpu_panel_power_backlight_on_delay" = "2000" # 200ms
register "gpu_panel_power_backlight_off_delay" = "2000" # 200ms
# Set backlight PWM values for eDP
register "gpu_cpu_backlight" = "0x00000200"
register "gpu_pch_backlight" = "0x04000000"
device cpu_cluster 0 on
chip cpu/intel/socket_rPGA989
device lapic 0 on end
end
chip cpu/intel/model_206ax
# Magic APIC ID to locate this chip
device lapic 0xACAC off end
# Coordinate with HW_ALL
register "pstate_coord_type" = "0xfe"
register "c1_acpower" = "1" # ACPI(C1) = MWAIT(C1)
register "c2_acpower" = "3" # ACPI(C2) = MWAIT(C3)
register "c3_acpower" = "5" # ACPI(C3) = MWAIT(C7)
register "c1_battery" = "1" # ACPI(C1) = MWAIT(C1)
register "c2_battery" = "3" # ACPI(C2) = MWAIT(C3)
register "c3_battery" = "5" # ACPI(C3) = MWAIT(C7)
end
end
device domain 0 on
subsystemid 0x1ae0 0xc000 inherit
device pci 00.0 on end # host bridge
device pci 02.0 on end # vga controller
chip southbridge/intel/bd82x6x # Intel Series 6 Cougar Point PCH
register "pirqa_routing" = "0x8b"
register "pirqb_routing" = "0x8a"
register "pirqc_routing" = "0x8b"
register "pirqd_routing" = "0x8b"
register "pirqe_routing" = "0x80"
register "pirqf_routing" = "0x80"
register "pirqg_routing" = "0x80"
register "pirqh_routing" = "0x80"
# GPI routing
# 0 No effect (default)
# 1 SMI# (if corresponding ALT_GPI_SMI_EN bit is also set)
# 2 SCI (if corresponding GPIO_EN bit is also set)
register "alt_gp_smi_en" = "0x0100"
register "gpi7_routing" = "2"
register "gpi8_routing" = "1"
register "ide_legacy_combined" = "0x0"
register "sata_ahci" = "0x1"
register "sata_port_map" = "0x1"
register "sata_port0_gen3_tx" = "0x00880a7f"
# EC range is 0x800-0x9ff
# Please note: you MUST not change this unless
# you also change romstage.c:pch_enable_lpc
register "gen1_dec" = "0x00fc0801"
register "gen2_dec" = "0x00fc0901"
# Enable zero-based linear PCIe root port functions
register "pcie_port_coalesce" = "1"
device pci 16.0 on end # Management Engine Interface 1
device pci 16.1 off end # Management Engine Interface 2
device pci 16.2 off end # Management Engine IDE-R
device pci 16.3 off end # Management Engine KT
device pci 19.0 off end # Intel Gigabit Ethernet
device pci 1a.0 on end # USB2 EHCI #2
device pci 1b.0 on end # High Definition Audio
device pci 1c.0 off end # PCIe Port #1 (WLAN remapped)
device pci 1c.1 off end # PCIe Port #2
device pci 1c.2 on end # PCIe Port #3 (WLAN actual)
device pci 1c.3 off end # PCIe Port #4
device pci 1c.4 off end # PCIe Port #5
device pci 1c.5 off end # PCIe Port #6
device pci 1c.6 off end # PCIe Port #7
device pci 1c.7 off end # PCIe Port #8
device pci 1d.0 on end # USB2 EHCI #1
device pci 1e.0 off end # PCI bridge
device pci 1f.0 on
chip ec/google/chromeec
# We only have one init function that
# we need to call to initialize the
# keyboard part of the EC.
device pnp ff.1 on # dummy address
end
end
end # LPC bridge
device pci 1f.2 on end # SATA Controller 1
device pci 1f.3 on end # SMBus
device pci 1f.5 off end # SATA Controller 2
device pci 1f.6 on end # Thermal
end
end
end

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src/mainboard/google/link/dsdt.asl Normal file
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/*
* This file is part of the coreboot project.
*
* Copyright (C) 2007-2009 coresystems GmbH
* Copyright (C) 2011 Google Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
DefinitionBlock(
"dsdt.aml",
"DSDT",
0x02, // DSDT revision: ACPI v2.0
"COREv4", // OEM id
"COREBOOT", // OEM table id
0x20110725 // OEM revision
)
{
// Some generic macros
#include "acpi/platform.asl"
#include "acpi/mainboard.asl"
// global NVS and variables
#include <southbridge/intel/bd82x6x/acpi/globalnvs.asl>
// General Purpose Events
//#include "acpi/gpe.asl"
#include "acpi/thermal.asl"
#include <cpu/intel/model_206ax/acpi/cpu.asl>
Scope (\_SB) {
Device (PCI0)
{
#include <northbridge/intel/sandybridge/acpi/sandybridge.asl>
#include <southbridge/intel/bd82x6x/acpi/pch.asl>
}
}
#include "acpi/chromeos.asl"
#include <vendorcode/google/chromeos/acpi/chromeos.asl>
/* Chipset specific sleep states */
#include <southbridge/intel/bd82x6x/acpi/sleepstates.asl>
}

52
src/mainboard/google/link/ec.c Normal file
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/*
* This file is part of the coreboot project.
*
* Copyright (C) 2012 Google Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
#include <arch/acpi.h>
#include <vendorcode/google/chromeos/chromeos.h>
#include <types.h>
#include <console/console.h>
#include <ec/google/chromeec/ec.h>
#include "ec.h"
void link_ec_init(void)
{
printk(BIOS_DEBUG, "link_ec_init\n");
post_code(0xf0);
/* Restore SCI event mask on resume. */
if (acpi_slp_type == 3) {
google_chromeec_log_events(LINK_EC_LOG_EVENTS |
LINK_EC_S3_WAKE_EVENTS);
/* Disable SMI and wake events */
google_chromeec_set_smi_mask(0);
/* Clear pending events */
while (google_chromeec_get_event() != 0);
google_chromeec_set_sci_mask(LINK_EC_SCI_EVENTS);
} else {
google_chromeec_log_events(LINK_EC_LOG_EVENTS |
LINK_EC_S5_WAKE_EVENTS);
}
/* Clear wake events, these are enabled on entry to sleep */
google_chromeec_set_wake_mask(0);
post_code(0xf1);
}

62
src/mainboard/google/link/ec.h Normal file
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/*
* This file is part of the coreboot project.
*
* Copyright (C) 2011 Google Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
#ifndef LINK_EC_H
#define LINK_EC_H
#include <ec/google/chromeec/ec_commands.h>
#define EC_SCI_GPI 7 /* GPIO7 is EC_SCI# */
#define EC_SMI_GPI 8 /* GPIO8 is EC_SMI# */
#define LINK_EC_SCI_EVENTS \
(EC_HOST_EVENT_MASK(EC_HOST_EVENT_LID_CLOSED) |\
EC_HOST_EVENT_MASK(EC_HOST_EVENT_LID_OPEN) |\
EC_HOST_EVENT_MASK(EC_HOST_EVENT_AC_CONNECTED) |\
EC_HOST_EVENT_MASK(EC_HOST_EVENT_AC_DISCONNECTED) |\
EC_HOST_EVENT_MASK(EC_HOST_EVENT_BATTERY_LOW) |\
EC_HOST_EVENT_MASK(EC_HOST_EVENT_BATTERY_CRITICAL) |\
EC_HOST_EVENT_MASK(EC_HOST_EVENT_BATTERY) |\
EC_HOST_EVENT_MASK(EC_HOST_EVENT_THERMAL_THRESHOLD) |\
EC_HOST_EVENT_MASK(EC_HOST_EVENT_THERMAL_OVERLOAD) |\
EC_HOST_EVENT_MASK(EC_HOST_EVENT_USB_CHARGER))
#define LINK_EC_SMI_EVENTS \
(EC_HOST_EVENT_MASK(EC_HOST_EVENT_LID_CLOSED))
/* EC can wake from S5 with lid or power button */
#define LINK_EC_S5_WAKE_EVENTS \
(EC_HOST_EVENT_MASK(EC_HOST_EVENT_LID_OPEN) |\
EC_HOST_EVENT_MASK(EC_HOST_EVENT_POWER_BUTTON))
/* EC can wake from S3 with lid or power button or key press */
#define LINK_EC_S3_WAKE_EVENTS \
(LINK_EC_S5_WAKE_EVENTS |\
EC_HOST_EVENT_MASK(EC_HOST_EVENT_KEY_PRESSED))
/* Log EC wake events plus EC shutdown events */
#define LINK_EC_LOG_EVENTS \
(EC_HOST_EVENT_MASK(EC_HOST_EVENT_THERMAL_SHUTDOWN) |\
EC_HOST_EVENT_MASK(EC_HOST_EVENT_BATTERY_SHUTDOWN))
#ifndef __ACPI__
extern void link_ec_init(void);
#endif
#endif // LINK_EC_H

32
src/mainboard/google/link/elpida_4Gb_1600_x16.spd.hex Normal file
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92 10 0b 03 04 19 02 02
03 52 01 08 0a 00 fe 00
69 78 69 3c 69 11 18 81
20 08 3c 3c 01 40 83 81
00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00
00 00 00 00 0f 11 42 00
00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00
00 00 00 00 00 02 fe 00
11 52 00 00 00 07 7f 37
45 42 4a 32 30 55 47 36
45 42 55 30 2d 47 4e 2d
46 20 30 20 02 fe 00 00
00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00

166
src/mainboard/google/link/fadt.c Normal file
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/*
* This file is part of the coreboot project.
*
* Copyright (C) 2007-2009 coresystems GmbH
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
#include <string.h>
#include <device/pci.h>
#include <arch/acpi.h>
/* FIXME: This needs to go into a separate .h file
* to be included by the ich7 smi handler, ich7 smi init
* code and the mainboard fadt.
*/
#define APM_CNT 0xb2
#define CST_CONTROL 0x85
#define PST_CONTROL 0x80
#define ACPI_DISABLE 0x1e
#define ACPI_ENABLE 0xe1
#define GNVS_UPDATE 0xea
void acpi_create_fadt(acpi_fadt_t * fadt, acpi_facs_t * facs, void *dsdt)
{
acpi_header_t *header = &(fadt->header);
u16 pmbase = pci_read_config16(dev_find_slot(0, PCI_DEVFN(0x1f,0)),
0x40) & 0xfffe;
memset((void *) fadt, 0, sizeof(acpi_fadt_t));
memcpy(header->signature, "FACP", 4);
header->length = sizeof(acpi_fadt_t);
header->revision = 3;
memcpy(header->oem_id, OEM_ID, 6);
memcpy(header->oem_table_id, ACPI_TABLE_CREATOR, 8);
memcpy(header->asl_compiler_id, "CORE", 4);
header->asl_compiler_revision = 1;
fadt->firmware_ctrl = (unsigned long) facs;
fadt->dsdt = (unsigned long) dsdt;
fadt->model = 1;
fadt->preferred_pm_profile = PM_DESKTOP;
fadt->sci_int = 0x9;
fadt->smi_cmd = APM_CNT;
fadt->acpi_enable = ACPI_ENABLE;
fadt->acpi_disable = ACPI_DISABLE;
fadt->s4bios_req = 0x0;
fadt->pstate_cnt = 0;
fadt->pm1a_evt_blk = pmbase;
fadt->pm1b_evt_blk = 0x0;
fadt->pm1a_cnt_blk = pmbase + 0x4;
fadt->pm1b_cnt_blk = 0x0;
fadt->pm2_cnt_blk = pmbase + 0x50;
fadt->pm_tmr_blk = pmbase + 0x8;
fadt->gpe0_blk = pmbase + 0x20;
fadt->gpe1_blk = 0;
fadt->pm1_evt_len = 4;
fadt->pm1_cnt_len = 2;
fadt->pm2_cnt_len = 1;
fadt->pm_tmr_len = 4;
fadt->gpe0_blk_len = 16;
fadt->gpe1_blk_len = 0;
fadt->gpe1_base = 0;
fadt->cst_cnt = 0;
fadt->p_lvl2_lat = 1;
fadt->p_lvl3_lat = 87;
fadt->flush_size = 1024;
fadt->flush_stride = 16;
fadt->duty_offset = 1;
fadt->duty_width = 0;
fadt->day_alrm = 0xd;
fadt->mon_alrm = 0x00;
fadt->century = 0x00;
fadt->iapc_boot_arch = ACPI_FADT_LEGACY_DEVICES | ACPI_FADT_8042;
fadt->flags = ACPI_FADT_WBINVD | ACPI_FADT_C1_SUPPORTED |
ACPI_FADT_C2_MP_SUPPORTED | ACPI_FADT_SLEEP_BUTTON |
ACPI_FADT_RESET_REGISTER | ACPI_FADT_SEALED_CASE |
ACPI_FADT_S4_RTC_WAKE | ACPI_FADT_PLATFORM_CLOCK;
fadt->reset_reg.space_id = 1;
fadt->reset_reg.bit_width = 8;
fadt->reset_reg.bit_offset = 0;
fadt->reset_reg.resv = 0;
fadt->reset_reg.addrl = 0xcf9;
fadt->reset_reg.addrh = 0;
fadt->reset_value = 6;
fadt->x_firmware_ctl_l = (unsigned long)facs;
fadt->x_firmware_ctl_h = 0;
fadt->x_dsdt_l = (unsigned long)dsdt;
fadt->x_dsdt_h = 0;
fadt->x_pm1a_evt_blk.space_id = 1;
fadt->x_pm1a_evt_blk.bit_width = 32;
fadt->x_pm1a_evt_blk.bit_offset = 0;
fadt->x_pm1a_evt_blk.resv = 0;
fadt->x_pm1a_evt_blk.addrl = pmbase;
fadt->x_pm1a_evt_blk.addrh = 0x0;
fadt->x_pm1b_evt_blk.space_id = 1;
fadt->x_pm1b_evt_blk.bit_width = 0;
fadt->x_pm1b_evt_blk.bit_offset = 0;
fadt->x_pm1b_evt_blk.resv = 0;
fadt->x_pm1b_evt_blk.addrl = 0x0;
fadt->x_pm1b_evt_blk.addrh = 0x0;
fadt->x_pm1a_cnt_blk.space_id = 1;
fadt->x_pm1a_cnt_blk.bit_width = 16;
fadt->x_pm1a_cnt_blk.bit_offset = 0;
fadt->x_pm1a_cnt_blk.resv = 0;
fadt->x_pm1a_cnt_blk.addrl = pmbase + 0x4;
fadt->x_pm1a_cnt_blk.addrh = 0x0;
fadt->x_pm1b_cnt_blk.space_id = 1;
fadt->x_pm1b_cnt_blk.bit_width = 0;
fadt->x_pm1b_cnt_blk.bit_offset = 0;
fadt->x_pm1b_cnt_blk.resv = 0;
fadt->x_pm1b_cnt_blk.addrl = 0x0;
fadt->x_pm1b_cnt_blk.addrh = 0x0;
fadt->x_pm2_cnt_blk.space_id = 1;
fadt->x_pm2_cnt_blk.bit_width = 8;
fadt->x_pm2_cnt_blk.bit_offset = 0;
fadt->x_pm2_cnt_blk.resv = 0;
fadt->x_pm2_cnt_blk.addrl = pmbase + 0x50;
fadt->x_pm2_cnt_blk.addrh = 0x0;
fadt->x_pm_tmr_blk.space_id = 1;
fadt->x_pm_tmr_blk.bit_width = 32;
fadt->x_pm_tmr_blk.bit_offset = 0;
fadt->x_pm_tmr_blk.resv = 0;
fadt->x_pm_tmr_blk.addrl = pmbase + 0x8;
fadt->x_pm_tmr_blk.addrh = 0x0;
fadt->x_gpe0_blk.space_id = 1;
fadt->x_gpe0_blk.bit_width = 64;
fadt->x_gpe0_blk.bit_offset = 0;
fadt->x_gpe0_blk.resv = 0;
fadt->x_gpe0_blk.addrl = pmbase + 0x20;
fadt->x_gpe0_blk.addrh = 0x0;
fadt->x_gpe1_blk.space_id = 1;
fadt->x_gpe1_blk.bit_width = 0;
fadt->x_gpe1_blk.bit_offset = 0;
fadt->x_gpe1_blk.resv = 0;
fadt->x_gpe1_blk.addrl = 0x0;
fadt->x_gpe1_blk.addrh = 0x0;
header->checksum =
acpi_checksum((void *) fadt, header->length);
}

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src/mainboard/google/link/gpio.h Normal file
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/*
* This file is part of the coreboot project.
*
* Copyright (C) 2011 Google Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
#ifndef LINK_GPIO_H
#define LINK_GPIO_H
#include "southbridge/intel/bd82x6x/gpio.h"
const struct pch_gpio_set1 pch_gpio_set1_mode = {
.gpio0 = GPIO_MODE_GPIO, /* NMI_DBG# */
.gpio3 = GPIO_MODE_GPIO, /* ALS_INT# */
.gpio5 = GPIO_MODE_GPIO, /* SIM_DET */
.gpio7 = GPIO_MODE_GPIO, /* EC_SCI# */
.gpio8 = GPIO_MODE_GPIO, /* EC_SMI# */
.gpio9 = GPIO_MODE_GPIO, /* RECOVERY# */
.gpio10 = GPIO_MODE_GPIO, /* SPD vector D3 */
.gpio11 = GPIO_MODE_GPIO, /* smbalert#, let's keep it initialized */
.gpio12 = GPIO_MODE_GPIO, /* TP_INT# */
.gpio14 = GPIO_MODE_GPIO, /* Touch_INT_L */
.gpio15 = GPIO_MODE_GPIO, /* EC_LID_OUT# (EC_WAKE#) */
.gpio21 = GPIO_MODE_GPIO, /* EC_IN_RW */
.gpio24 = GPIO_MODE_GPIO, /* DDR3L_EN */
.gpio28 = GPIO_MODE_GPIO, /* SLP_ME_CSW_DEV# */
};
const struct pch_gpio_set1 pch_gpio_set1_direction = {
.gpio0 = GPIO_DIR_INPUT,
.gpio3 = GPIO_DIR_INPUT,
.gpio5 = GPIO_DIR_INPUT,
.gpio7 = GPIO_DIR_INPUT,
.gpio8 = GPIO_DIR_INPUT,
.gpio9 = GPIO_DIR_INPUT,
.gpio10 = GPIO_DIR_INPUT,
.gpio11 = GPIO_DIR_INPUT,
.gpio12 = GPIO_DIR_INPUT,
.gpio14 = GPIO_DIR_INPUT,
.gpio15 = GPIO_DIR_INPUT,
.gpio21 = GPIO_DIR_INPUT,
.gpio24 = GPIO_DIR_OUTPUT,
.gpio28 = GPIO_DIR_INPUT,
};
const struct pch_gpio_set1 pch_gpio_set1_level = {
.gpio1 = GPIO_LEVEL_HIGH,
.gpio6 = GPIO_LEVEL_HIGH,
.gpio24 = GPIO_LEVEL_LOW,
};
const struct pch_gpio_set1 pch_gpio_set1_invert = {
.gpio7 = GPIO_INVERT,
.gpio8 = GPIO_INVERT,
.gpio12 = GPIO_INVERT,
.gpio14 = GPIO_INVERT,
.gpio15 = GPIO_INVERT,
};
const struct pch_gpio_set2 pch_gpio_set2_mode = {
.gpio36 = GPIO_MODE_GPIO, /* W_DISABLE_L */
.gpio41 = GPIO_MODE_GPIO, /* SPD vector D0 */
.gpio42 = GPIO_MODE_GPIO, /* SPD vector D1 */
.gpio43 = GPIO_MODE_GPIO, /* SPD vector D2 */
.gpio57 = GPIO_MODE_GPIO, /* PCH_SPI_WP_D */
.gpio60 = GPIO_MODE_GPIO, /* DRAMRST_CNTRL_PCH */
};
const struct pch_gpio_set2 pch_gpio_set2_direction = {
.gpio36 = GPIO_DIR_OUTPUT,
.gpio41 = GPIO_DIR_INPUT,
.gpio42 = GPIO_DIR_INPUT,
.gpio43 = GPIO_DIR_INPUT,
.gpio57 = GPIO_DIR_INPUT,
.gpio60 = GPIO_DIR_OUTPUT,
};
const struct pch_gpio_set2 pch_gpio_set2_level = {
.gpio36 = GPIO_LEVEL_HIGH,
.gpio60 = GPIO_LEVEL_HIGH,
};
const struct pch_gpio_set3 pch_gpio_set3_mode = {
};
const struct pch_gpio_set3 pch_gpio_set3_direction = {
};
const struct pch_gpio_set3 pch_gpio_set3_level = {
};
const struct pch_gpio_map link_gpio_map = {
.set1 = {
.mode = &pch_gpio_set1_mode,
.direction = &pch_gpio_set1_direction,
.level = &pch_gpio_set1_level,
.invert = &pch_gpio_set1_invert,
},
.set2 = {
.mode = &pch_gpio_set2_mode,
.direction = &pch_gpio_set2_direction,
.level = &pch_gpio_set2_level,
},
.set3 = {
.mode = &pch_gpio_set3_mode,
.direction = &pch_gpio_set3_direction,
.level = &pch_gpio_set3_level,
},
};
#endif

181
src/mainboard/google/link/hda_verb.h Normal file
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/*
* This file is part of the coreboot project.
*
* Copyright (C) 2011 Google Inc.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
static const u32 mainboard_cim_verb_data[] = {
/* coreboot specific header */
0x11020011, // Codec Vendor / Device ID: Creative CA0132
0x144dc0c2, // Subsystem ID
0x00000014, // Number of jacks + Number of Malcolm setup blocks.
/* Malcolm Setup */
0x01570d09,
0x01570c23,
0x01570a01,
0x01570df0,
0x01570efe,
0x01570775,
0x015707d3,
0x01570709,
0x01570753,
0x015707d4,
0x015707ef,
0x01570775,
0x015707d3,
0x01570709,
0x01570702,
0x01570737,
0x01570778,
0x01553cce,
0x015575c9,
0x01553dce,
0x0155b7c9,
0x01570de8,
0x01570efe,
0x01570702,
0x01570768,
0x01570762,
0x01553ace,
0x015546c9,
0x01553bce,
0x0155e8c9,
0x01570d49,
0x01570c88,
0x01570d20,
0x01570e19,
0x01570700,
0x01571a05,
0x01571b29,
0x01571a04,
0x01571b29,
0x01570a01,
/* Pin Widget Verb Table */
/* NID 0x01, HDA Codec Subsystem ID Verb Table: 0x144DC0C2 */
0x001720c2,
0x001721c0,
0x0017224d,
0x00172314,
/* Pin Complex (NID 0x0B) Port-G Analog Unknown Speaker at Int N/A */
0x00b71cf0,
0x00b71d00,
0x00b71e17,
0x00b71f90,
/* Pin Complex (NID 0x0C) N/C */
0x00c71cf0,
0x00c71d00,
0x00c71ef0,
0x00c71f70,
/* Pin Complex (NID 0x0D) N/C */
0x00d71cf0,
0x00d71d00,
0x00d71ef0,
0x00d71f70,
/* Pin Complex (NID 0x0E) N/C */
0x00e71cf0,
0x00e71d00,
0x00e71ef0,
0x00e71f70,
/* Pin Complex (NID 0x0F) N/C */
0x00f71cf0,
0x00f71d00,
0x00f71ef0,
0x00f71f70,
/* Pin Complex (NID 0x10) Port-D 1/8 Black HP Out at Ext Left */
0x01071cf0,
0x01071d10,
0x01071e21,
0x01071f03,
/* Pin Complex (NID 0x11) Port-B Click Mic */
0x01171cf0,
0x01171d00,
0x01171ea7,
0x01171f90,
/* Pin Complex (NID 0x12) Port-C Combo Jack Mic or D-Mic */
0x01271cf0,
0x01271d10,
0x01271ea1,
0x01271f03,
/* Pin Complex (NID 0x13) What you hear */
0x01371cf0,
0x01371d00,
0x01371ed6,
0x01371f90,
/* coreboot specific header */
0x80862806, // Codec Vendor / Device ID: Intel CougarPoint HDMI
0x80860101, // Subsystem ID
0x00000004, // Number of jacks
/* NID 0x01, HDA Codec Subsystem ID Verb Table: 0x80860101 */
0x30172001,
0x30172101,
0x30172286,
0x30172380,
/* Pin Complex (NID 0x05) Digital Out at Int HDMI */
0x30571c10,
0x30571d00,
0x30571e56,
0x30571f18,
/* Pin Complex (NID 0x06) Digital Out at Int HDMI */
0x30671c20,
0x30671d00,
0x30671e56,
0x30671f18,
/* Pin Complex (NID 0x07) Digital Out at Int HDMI */
0x30771c30,
0x30771d00,
0x30771e56,
0x30771f18
};
static const u32 mainboard_pc_beep_verbs[] = {
0x00170500, /* power up codec */
0x00270500, /* power up DAC */
0x00b70500, /* power up speaker */
0x00b70740, /* enable speaker out */
0x00b78d00, /* enable EAPD pin */
0x00b70c02, /* set EAPD pin */
0x0143b013, /* beep volume */
};
static const u32 mainboard_pc_beep_verbs_size =
sizeof(mainboard_pc_beep_verbs) / sizeof(mainboard_pc_beep_verbs[0]);

259
src/mainboard/google/link/i915.c Normal file
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/*
* This file is part of the coreboot project.
*
* Copyright (C) 2012 Google Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
#include <types.h>
#include <string.h>
#include <device/device.h>
#include <device/device.h>
#include <device/pci_def.h>
#include <device/pci_ops.h>
#include <console/console.h>
#include <delay.h>
#include <pc80/mc146818rtc.h>
#include <arch/acpi.h>
#include <arch/io.h>
#include <arch/interrupt.h>
#include <arch/coreboot_tables.h>
#include "hda_verb.h"
#include "onboard.h"
#include "ec.h"
#include <southbridge/intel/bd82x6x/pch.h>
#include <smbios.h>
#include <device/pci.h>
#include <ec/google/chromeec/ec.h>
#include <cbfs_core.h>
#include <cpu/x86/tsc.h>
#include <cpu/x86/cache.h>
#include <cpu/x86/mtrr.h>
#include <cpu/amd/mtrr.h>
#include <cpu/x86/msr.h>
#include "i915io.h"
enum {
vmsg = 1, vio = 2, vspin = 4,
};
static int verbose = 0;
static unsigned int *mmio;
static unsigned int graphics;
static unsigned short addrport;
static unsigned short dataport;
static unsigned int physbase;
extern int oprom_is_loaded;
#define READ32(addr) io_i915_READ32(addr)
#define WRITE32(val, addr) io_i915_WRITE32(val, addr)
static unsigned long io_i915_READ32(unsigned long addr)
{
unsigned long val;
outl(addr, addrport);
val = inl(dataport);
return val;
}
static void io_i915_WRITE32(unsigned long val, unsigned long addr)
{
outl(addr, addrport);
outl(val, dataport);
}
/*
2560
4 words per
4 *p
10240
4k bytes per page
4096/p
2.50
1700 lines
1700 * p
4250.00
PTEs
*/
static void
setgtt(int start, int end, unsigned long base, int inc)
{
int i;
for(i = start; i < end; i++){
u32 word = base + i*inc;
WRITE32(word|1,(i*4)|1);
}
}
static char *regname(unsigned long addr)
{
static char name[16];
sprintf(name, "0x%lx", addr);
return name;
}
static unsigned long tickspermicrosecond = 1795;
static unsigned long long globalstart;
static unsigned long
microseconds(unsigned long long start, unsigned long long end)
{
unsigned long ret;
ret = ((end - start)/tickspermicrosecond);
return ret;
}
static unsigned long globalmicroseconds(void)
{
return microseconds(globalstart, rdtscll());
}
extern struct iodef iodefs[];
static int i915_init_done = 0;
int vbe_mode_info_valid(void);
int vbe_mode_info_valid(void)
{
return i915_init_done;
}
void fill_lb_framebuffer(struct lb_framebuffer *framebuffer);
void fill_lb_framebuffer(struct lb_framebuffer *framebuffer)
{
printk(BIOS_SPEW, "fill_lb_framebuffer: graphics is %p\n", (void *)graphics);
framebuffer->physical_address = graphics;
framebuffer->x_resolution = 2560;
framebuffer->y_resolution = 1700;
framebuffer->bytes_per_line = 10240;
framebuffer->bits_per_pixel = 32;
framebuffer->red_mask_pos = 16;
framebuffer->red_mask_size = 8;
framebuffer->green_mask_pos = 8;
framebuffer->green_mask_size = 8;
framebuffer->blue_mask_pos = 0;
framebuffer->blue_mask_size = 8;
framebuffer->reserved_mask_pos = 0;
framebuffer->reserved_mask_size = 0;
}
int i915lightup(unsigned int physbase, unsigned int iobase, unsigned int mmio,
unsigned int gfx);
int i915lightup(unsigned int pphysbase,
unsigned int piobase,
unsigned int pmmio,
unsigned int pgfx)
{
int i, prev = 0;
struct iodef *id, *lastidread = 0;
unsigned long u, t;
static unsigned long times[4096];
mmio = (void *)pmmio;
addrport = piobase;
dataport = addrport + 4;
physbase = pphysbase;
graphics = pgfx;
printk(BIOS_SPEW,
"i915lightup: graphics %p mmio %p"
"addrport %04x physbase %08x\n",
(void *)graphics, mmio, addrport, physbase);
globalstart = rdtscll();
/* state machine! */
for(i = 0, id = iodefs; id->op; i++, id++){
switch(id->op){
case M:
if (verbose & vmsg) printk(BIOS_SPEW, "%ld: %s\n",
globalmicroseconds(), id->msg);
break;
case R:
u = READ32(id->addr);
if (verbose & vio)printk(BIOS_SPEW, "%s: Got %08lx, expect %08lx\n",
regname(id->addr), u, id->data);
/* we're looking for something. */
if (lastidread->addr == id->addr){
/* they're going to be polling.
* just do it 1000 times
*/
for(t = 0; t < 1000 && id->data != u; t++){
u = READ32(id->addr);
}
if (verbose & vspin) printk(BIOS_SPEW,
"%s: # loops %ld got %08lx want %08lx\n",
regname(id->addr),
t, u, id->data);
}
lastidread = id;
break;
case W:
if (verbose & vio)printk(BIOS_SPEW, "%s: outl %08lx\n", regname(id->addr),
id->data);
WRITE32(id->data, id->addr);
if (id->addr == PCH_PP_CONTROL){
switch(id->data & 0xf){
case 8: break;
case 7: break;
default: udelay(100000);
}
}
break;
case V:
if (id->count < 8){
prev = verbose;
verbose = id->count;
} else {
verbose = prev;
}
break;
case I:
break;
default:
printk(BIOS_SPEW, "BAD TABLE, opcode %d @ %d\n", id->op, i);
return -1;
}
if (id->udelay)
udelay(id->udelay);
times[i] = globalmicroseconds();
}
/* optional, we don't even want to take timestamp overhead
* if we can avoid it. */
if (0)
for(i = 0, id = iodefs; id->op; i++, id++){
switch(id->op){
case R:
printk(BIOS_SPEW, "%ld: R %08lx\n", times[i], id->addr);
break;
case W:
printk(BIOS_SPEW, "%ld: W %08lx %08lx\n", times[i],
id->addr, id->data);
break;
}
}
setgtt(0, 4520, physbase, 4096);
printk(BIOS_SPEW, "memset %p to 0 for %d bytes\n",
(void *)graphics, 4520*4096);
memset((void *)graphics, 0, 4520*4096);
printk(BIOS_SPEW, "%ld microseconds\n", globalmicroseconds());
i915_init_done = 1;
oprom_is_loaded = 1;
return 0;
}

3878
src/mainboard/google/link/i915_reg.h Normal file
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755
src/mainboard/google/link/i915io.c Normal file
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@ -0,0 +1,755 @@
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2012 Google Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
#include "i915io.h"
struct iodef iodefs[] = {
{V,0,},
//{V, 7, },
{W, 1, "", PCH_GMBUS0, 0x00000000, },
{R, 1, "", PP_ON_DELAYS, 0x00000000, },
{R, 1, "", PP_OFF_DELAYS, 0x00000000, },
{W, 1, "", PP_ON_DELAYS, 0x019007d0, },
{W, 1, "", PP_OFF_DELAYS, 0x015e07d0, },
{M, 1, "[drm:intel_detect_pch], Found PatherPoint PCH"},
{M, 1, "[drm:i915_load_modeset_init], failed to find VBIOS tables"},
{R, 50, "", 0x130040, 0x00000001, 10},
{W, 1, "", 0xa188, 0x00010001, },
{R, 1, "", 0xa188, 0x00010001, },
{R, 1, "", 0x130040, 0x00000001, },
{R, 1, "", 0x13805c, 0x40000000, },
{R, 1, "", 0xa180, 0x84100020, },
{W, 1, "", 0xa188, 0x00010000, },
{R, 1, "", 0x120000, 0x00000000, },
{M, 1, "[drm:intel_init_display], Using MT version of forcewake"},
{R, 1, "", 0x145d10, 0x2010040c, },
{M, 1, "[drm:intel_modeset_init], 3 display pipes available."},
{R, 1, "", _PIPEACONF, 0x00000000, },
{W, 1, "", _PIPEACONF, 0x00000000, },
{R, 1, "", _PIPEBCONF, 0x00000000, },
{W, 1, "", _PIPEBCONF, 0x00000000, },
{R, 1, "", 0x72008, 0x00000000, },
{W, 1, "", 0x72008, 0x00000000, },
{R, 1, "", _PIPEACONF, 0x00000000, },
{W, 1, "", _PIPEACONF, 0x00000000, },
{R, 1, "", _PIPEBCONF, 0x00000000, },
{W, 1, "", _PIPEBCONF, 0x00000000, },
{R, 1, "", 0x72008, 0x00000000, },
{W, 1, "", 0x72008, 0x00000000, },
{R, 1, "", _PIPEACONF, 0x00000000, },
{W, 1, "", _PIPEACONF, 0x00000000, },
{R, 1, "", _PIPEBCONF, 0x00000000, },
{W, 1, "", _PIPEBCONF, 0x00000000, },
{R, 1, "", 0x72008, 0x00000000, },
{W, 1, "", 0x72008, 0x00000000, 300},
{W, 1, "", CPU_VGACNTRL, 0x80000000, },
{R, 1, "", CPU_VGACNTRL, 0x80000000, },
{R, 1, "", 0x64000, 0x0000001c, },
{R, 1, "", PCH_PP_ON_DELAYS, 0x47d007d0, },
{R, 1, "", PCH_PP_OFF_DELAYS, 0x01f407d0, },
{R, 1, "", PCH_PP_DIVISOR, 0x00186906, },
{M, 1, "[drm:intel_dp_init], cur t1_t3 2000 t8 2000 t9 2000 t10 500"
"t11_t12 6000"},
{M, 1, "[drm:intel_dp_init], vbt t1_t3 0 t8 0 t9 0 t10 0 t11_t12 0"},
{M, 1, "[drm:intel_dp_init], panel power up delay 200,"
"power down delay 50, power cycle delay 600"},
{M, 1, "[drm:intel_dp_init], backlight on delay 200, off delay 200"},
{M, 1, "[drm:ironlake_edp_panel_vdd_on], Turn eDP VDD on"},
{R, 1, "", PCH_PP_CONTROL, 0x00000000, },
{R, 1, "", PCH_PP_STATUS, 0x00000000, },
{M, 1, "[drm:ironlake_wait_panel_power_cycle], Wait for panel power cycle"},
{M, 1, "[drm:ironlake_wait_panel_status], R PCH_PP_CONTROL:00000000"},
{R, 2, "", PCH_PP_STATUS, 0x00000000, },
{R, 1, "", PCH_PP_CONTROL, 0x00000000, },
{W, 1, "", PCH_PP_CONTROL, 0xabcd0008, },
{R, 1, "", PCH_PP_CONTROL, 0xabcd0008, },
{M, 1, "[drm:ironlake_edp_panel_vdd_on], R PCH_PP_CONTROL:abcd0008"},
{R, 2, "", PCH_PP_STATUS, 0x00000000, },
{M, 1, "[drm:ironlake_edp_panel_vdd_on], eDP was not running"},
{R, 1, "", PCH_PP_STATUS, 0x00000000, },
{R, 1, "", PCH_PP_CONTROL, 0xabcd0008, },
{R, 1, "", PCH_PP_STATUS, 0x00000000, },
{R, 1, "", PCH_PP_CONTROL, 0xabcd0008, },
{R, 1, "", DPA_AUX_CH_CTL, 0x014300c8, },
{W, 1, "", DPA_AUX_CH_DATA1, 0x9000000e, },
{W, 1, "", DPA_AUX_CH_CTL, 0xd24500c8, },
{R, 2, "", DPA_AUX_CH_CTL, 0x814500c8, 100},
{R, 1, "", DPA_AUX_CH_CTL, 0x807500c8, 100},
{R, 1, "", DPA_AUX_CH_CTL, 0x810500c8, 100},
{R, 1, "", DPA_AUX_CH_CTL, 0x410500c8, },
{W, 1, "", DPA_AUX_CH_CTL, 0x530500c8, },
{R, 1, "", DPA_AUX_CH_DATA1, 0x00110a84, },
{R, 1, "", DPA_AUX_CH_DATA2, 0x41000001, },
{R, 1, "", DPA_AUX_CH_DATA3, 0xc0020000, },
{R, 1, "", DPA_AUX_CH_DATA4, 0x001f0000, },
{M, 1, "[drm:intel_dp_i2c_init], i2c_init DPDDC-A"},
{R, 1, "", PCH_PP_STATUS, 0x00000000, },
{R, 1, "", PCH_PP_CONTROL, 0xabcd0008, },
{R, 1, "", PCH_PP_STATUS, 0x00000000, },
{R, 1, "", PCH_PP_CONTROL, 0xabcd0008, },
{R, 1, "", DPA_AUX_CH_CTL, 0x010500c8, },
{W, 1, "", DPA_AUX_CH_DATA1, 0x40000000, },
{W, 1, "", DPA_AUX_CH_CTL, 0xd23500c8, },
{R, 2, "", DPA_AUX_CH_CTL, 0x810500c8, 100},
{R, 1, "", DPA_AUX_CH_CTL, 0x401500c8, },
{W, 1, "", DPA_AUX_CH_CTL, 0x521500c8, },
{R, 1, "", DPA_AUX_CH_DATA1, 0x00000000, },
{R, 1, "", PCH_PP_STATUS, 0x00000000, },
{R, 1, "", PCH_PP_CONTROL, 0xabcd0008, },
{R, 1, "", PCH_PP_STATUS, 0x00000000, },
{R, 1, "", PCH_PP_CONTROL, 0xabcd0008, },
{R, 1, "", DPA_AUX_CH_CTL, 0x001500c8, },
{W, 1, "", DPA_AUX_CH_DATA1, 0x00000000, },
{W, 1, "", DPA_AUX_CH_CTL, 0xd23500c8, },
{R, 2, "", DPA_AUX_CH_CTL, 0x801500c8, 100},
{R, 1, "", DPA_AUX_CH_CTL, 0x401500c8, },
{W, 1, "", DPA_AUX_CH_CTL, 0x521500c8, },
{R, 1, "", DPA_AUX_CH_DATA1, 0x00000000, },
{M, 1, "[drm:ironlake_edp_panel_vdd_off], Turn eDP VDD off 1"},
{R, 1, "", BLC_PWM_CPU_CTL, 0x000010ce, },
{M, 1, "[drm:intel_panel_get_backlight], get backlight PWM = 4302"},
{M, 1, "[drm:intel_dp_aux_ch], dp_aux_ch timeout status 0x5145003f"},
{M, 1, "[drm:intel_dp_i2c_aux_ch], aux_ch failed -110"},
{M, 1,
"[drm:ironlake_init_pch_refclk], has_panel 1 has_lvds 0 has_pch_edp 0"
"has_cpu_edp 1 has_ck505 0"},
{R, 1, "", PCH_DREF_CONTROL, 0x00000000, },
{M, 1, "[drm:ironlake_init_pch_refclk], Using SSC on panel"},
{W, 1, "", PCH_DREF_CONTROL, 0x00001402, },
{R, 1, "", PCH_DREF_CONTROL, 0x00001402, 200},
{M, 1, "[drm:ironlake_init_pch_refclk], Using SSC on eDP"},
{W, 1, "", PCH_DREF_CONTROL, 0x00005402, },
{R, 1, "", PCH_DREF_CONTROL, 0x00005402, 200},
{W, 1, "", ILK_DSPCLK_GATE, 0x10000000, },
{W, 1, "", WM3_LP_ILK, 0x00000000, },
{W, 1, "", WM2_LP_ILK, 0x00000000, },
{W, 1, "", WM1_LP_ILK, 0x00000000, },
{W, 1, "", 0x9404, 0x00002000, },
{W, 1, "", ILK_DSPCLK_GATE, 0x10000000, },
{W, 1, "", IVB_CHICKEN3, 0x00000024, },
{W, 1, "", 0x7010, 0x04000400, },
{W, 1, "", 0xb01c, 0x3c4fff8c, },
{W, 1, "", 0xb030, 0x20000000, },
{R, 1, "", 0x9030, 0x00000000, },
{W, 1, "", 0x9030, 0x00000800, },
{R, 1, "", _DSPACNTR, 0x00000000, },
{W, 1, "", _DSPACNTR, 0x00004000, },
{R, 1, "", _DSPAADDR, 0x00000000, },
{W, 1, "", _DSPAADDR, 0x00000000, },
{R, 1, "", _DSPASIZE+0xc, 0x00000000, },
{W, 1, "", _DSPASIZE+0xc, 0x00000000, },
{R, 1, "", _DSPBCNTR, 0x00000000, },
{W, 1, "", _DSPBCNTR, 0x00004000, },
{R, 1, "", _DSPBADDR, 0x00000000, },
{W, 1, "", _DSPBADDR, 0x00000000, },
{R, 1, "", _DSPBSURF, 0x00000000, },
{W, 1, "", _DSPBSURF, 0x00000000, },
{R, 1, "", _DVSACNTR, 0x00000000, },
{W, 1, "", _DVSACNTR, 0x00004000, },
{R, 1, "", _DVSALINOFF, 0x00000000, },
{W, 1, "", _DVSALINOFF, 0x00000000, },
{R, 1, "", _DVSASURF, 0x00000000, },
{W, 1, "", _DVSASURF, 0x00000000, },
{W, 1, "", SOUTH_DSPCLK_GATE_D, 0x20000000, },
{R, 1, "", SOUTH_CHICKEN2, 0x00000000, },
{W, 1, "", SOUTH_CHICKEN2, 0x00000001, },
{W, 1, "", _TRANSA_CHICKEN2, 0x80000000, },
{W, 1, "", _TRANSB_CHICKEN2, 0x80000000, },
/* to here, it works ok with v0 */
//{V, 7,},
{M, 1, "[drm:drm_edid_to_eld], ELD:no CEA Extension found"},
{M, 1, "[drm:drm_helper_probe_single_connector_modes], [CONNECTOR:6:eDP-1]"
"probed modes :"},
{M, 1, "[drm:drm_mode_debug_printmodeline],"
"Modeline 0:\"2560x1700\" 60 285250 2560 2608 2640 2720 1700 1703 1713 1749"
"0x48 0xa"},
{M, 1, "[drm:drm_setup_crtcs], "},
{M, 1, "[drm:drm_enable_connectors], connector 6 enabled? yes"},
{M, 1, "[drm:drm_setup_crtcs], picking CRTCs for 8192x8192 config"},
{M, 1, "[drm:drm_setup_crtcs], desired mode 2560x1700 set on crtc 3"},
{M, 1, "[drm:drm_helper_probe_single_connector_modes], [CONNECTOR:6:eDP-1]"},
{M, 1, "[drm:intel_dp_detect], DPCD:110a8441000001c0"},
{M, 1, "[drm:ironlake_edp_panel_vdd_on], Turn eDP VDD on"},
//{V, 7,},
{M, 1, "[drm:intel_dp_detect], DPCD:110a8441000001c0"},
{M, 1, "[drm:drm_enable_connectors], connector 6 enabled? yes"},
{M, 1, "[drm:intel_get_load_detect_pipe], [CONNECTOR:6:eDP-1],"
"[ENCODER:7:TMDS-7]"},
{M, 1, "[drm:intel_dp_mode_fixup], Display port link bw 0a lane count 4"
"clock 270000"},
{M, 1, "[drm:drm_crtc_helper_set_mode], [CRTC:3]"},
{R, 1, "", PCH_PP_STATUS, 0x00000000, },
{R, 1, "", PCH_PP_CONTROL, 0xabcd0008, },
{R, 1, "", PCH_PP_STATUS, 0x00000000, },
{R, 1, "", PCH_PP_CONTROL, 0xabcd0008, },
{R, 1, "", DPA_AUX_CH_CTL, 0x001500c8, },
{W, 1, "", DPA_AUX_CH_DATA1, 0x80060000, },
{W, 1, "", DPA_AUX_CH_DATA2, 0x01000000, },
{W, 1, "", DPA_AUX_CH_CTL, 0xd25500c8, },
{R, 2, "", DPA_AUX_CH_CTL, 0x801500c8, 100},
{R, 1, "", DPA_AUX_CH_CTL, 0x401500c8, },
{W, 1, "", DPA_AUX_CH_CTL, 0x521500c8, },
{R, 1, "", DPA_AUX_CH_DATA1, 0x00000000, },
{R, 1, "", 0x64000, 0x0000001c, },
{M, 1, "[drm:ironlake_edp_panel_vdd_off], Turn eDP VDD off 1"},
#if 0
/* I hope we never try to use this. It is left here as a documentation thing. */
/* SCALING HACK */
/* these were determined by reading registers.
* They should stretch the display.
* They don't.
* From u-boot? After vbios?
*/
{V, 7, },
{M, 1, "Turning on panel fitter (must be done before power cycle)"},
{W, 1, "Enabled,PIPEA,Hardcoded edge enhance", _PFA_CTL_1, 0x80800000, },
/* status: can't ever set vscale.
* Which may be why we get no display at all if we try. */
{W, 1, "stretch", _PFA_VSCALE, /*0x00004000*/0xffffffff, },
{W, 1, "stretch", _PFA_HSCALE, /*0x00004000*/0xffffffff, },
{W, 1, "2560x1700", _PFA_WIN_SZ, 0x0a0006a4, },
//{W, 1, "2560x1700", _PFA_WIN_SZ, 0x05000352, },
{W, 1, "@[0,0]", _PFA_WIN_POS, 0x00000000, },
{R, 1, "Vstretch", _PFA_VSCALE, 0x00004000, },
{R, 1, "Hstretch", _PFA_HSCALE, 0x00004000, },
{R, 1, "2560x1700", _PFA_WIN_SZ, 0x0a0006a4, },
{R, 1, "@[0,0]", _PFA_WIN_POS, 0x00000000, },
{R, 1, "Enabled,PIPEA,Hardcoded edge enhance", _PFA_CTL_1, 0x80800000, },
{V,0,},
/* END SCALING HACK */
#endif
{R, 2, "", PCH_DP_D, 0x00000004, },
{R, 1, "", _PIPEACONF, 0x00000000, },
{W, 1, "", _PIPEACONF, 0x00000040, },
{R, 1, "", _PIPEACONF, 0x00000040, },
{M, 1, "[drm:ironlake_crtc_mode_set], Mode for pipe 0:"},
{M, 1, "[drm:drm_mode_debug_printmodeline],"
"Modeline 0:\"2560x1700\" 60 285250 2560 2608 2640 2720 1700 1703 1713 1749"
" 0x48 0xa"},
{W, 1, "", _TRANSA_DATA_M1, 0x00000000, },
{W, 1, "", _TRANSA_DATA_N1, 0x00000000, },
{W, 1, "", _TRANSA_DP_LINK_M1, 0x00000000, },
{W, 1, "", _TRANSA_DP_LINK_N1, 0x00000000, },
{W, 1, "", _PCH_FPA1, 0x00020e08, },
{W, 1, "", _VSYNCSHIFT_A, 0x00000000, },
{W, 1, "", _HTOTAL_A, 0x0a9f09ff, },
{W, 1, "", _HBLANK_A, 0x0a9f09ff, },
{W, 1, "", _HSYNC_A, 0x0a4f0a2f, },
{W, 1, "", _VTOTAL_A, 0x06d406a3, },
{W, 1, "", _VBLANK_A, 0x06d406a3, },
{W, 1, "", _VSYNC_A, 0x06b006a6, },
{W, 1, "", _PIPEASRC, 0x09ff06a3, },
{W, 1, "", _PIPEA_DATA_M1, 0x7e4e58a4, },
{W, 1, "", _PIPEA_DATA_N1, 0x0083d600, },
{W, 1, "", _PIPEA_LINK_M1, 0x00045a42, },
{W, 1, "", _PIPEA_LINK_N1, 0x00041eb0, },
{M, 1, "[drm:ironlake_set_pll_edp], eDP PLL enable for clock 270000"},
{R, 1, "", 0x64000, 0x0000001c, },
{W, 1, "", 0x64000, 0x0000001c, },
{R, 1, "", 0x64000, 0x0000001c, 500},
{W, 1, "", _PIPEACONF, 0x00000050, },
{R, 1, "", _PIPEACONF, 0x00000050, },
{R, 1, "", _PIPEASTAT, 0x00000000, },
{W, 1, "", _PIPEASTAT, 0x00000002, },
{R, 4562, "", _PIPEASTAT, 0x00000000, },
{M, 1, "[drm:intel_wait_for_vblank], vblank wait timed out"},
{W, 1, "", _DSPACNTR, 0x40000000, },
{R, 2, "", _DSPACNTR, 0x40000000, },
{W, 1, "", _DSPACNTR, 0x58004000, },
{M, 1, "[drm:ironlake_update_plane], Writing base 00000000 00000000 0 0 10240"},
{W, 1, "", _DSPASTRIDE, 0x00002800, },
{W, 1, "", _DSPASIZE+0xc, 0x00000000, },
{W, 1, "", _DSPACNTR+0x24, 0x00000000, },
{W, 1, "", _DSPAADDR, 0x00000000, },
{R, 1, "", _DSPACNTR, 0x58004000, },
{R, 1, "", 0x145d10, 0x2010040c, },
{R, 1, "", WM0_PIPEA_ILK, 0x00783818, },
{W, 1, "", WM0_PIPEA_ILK, 0x00183806, },
{M, 1, "[drm:sandybridge_update_wm], FIFO watermarks For pipe A - plane 24,"
"cursor:6"},
{W, 1, "", WM3_LP_ILK, 0x00000000, },
{W, 1, "", WM2_LP_ILK, 0x00000000, },
{W, 1, "", WM1_LP_ILK, 0x00000000, },
{R, 1, "", 0x145d10, 0x2010040c, },
{M, 1, "[drm:ironlake_check_srwm], watermark 1:display plane 38, fbc lines 3,"
"cursor 6"},
{R, 1, "", 0x145d10, 0x2010040c, },
{W, 1, "", WM1_LP_ILK, 0x84302606, },
{R, 1, "", 0x145d10, 0x2010040c, },
{M, 1,"[drm:ironlake_check_srwm], watermark 2:display plane 145, fbc lines 3,"
"cursor 6"},
{R, 1, "", 0x145d10, 0x2010040c, },
{W, 1, "", WM2_LP_ILK, 0x90309106, },
{R, 1, "", 0x145d10, 0x2010040c, },
{M, 1, "[drm:ironlake_check_srwm], watermark 3:display plane 288, fbc lines 4,"
"cursor 10"},
{R, 1, "", 0x145d10, 0x2010040c, },
{W, 1, "", WM3_LP_ILK, 0xa041200a, },
{M, 1, "[drm:drm_crtc_helper_set_mode], [ENCODER:7:TMDS-7]"
"set [MODE:0:2560x1700]"},
{M, 1, "[drm:ironlake_edp_pll_on], "},
{R, 1, "", 0x64000, 0x0000001c, },
{W, 1, "", 0x64000, 0x0000401c, },
{R, 1, "", 0x64000, 0x0000401c, 200},
{R, 1, "", 0x64000, 0x0000401c, },
{R, 1, "", 0x145d10, 0x2010040c, },
{R, 1, "", WM0_PIPEA_ILK, 0x00183806, },
{W, 1, "", WM0_PIPEA_ILK, 0x00183806, },
{M, 1, "[drm:sandybridge_update_wm], FIFO watermarks For pipe A - plane 24,"
"cursor:6"},
{W, 1, "", WM3_LP_ILK, 0x00000000, },
{W, 1, "", WM2_LP_ILK, 0x00000000, },
{W, 1, "", WM1_LP_ILK, 0x00000000, },
{R, 1, "", 0x145d10, 0x2010040c, },
{M, 1, "[drm:ironlake_check_srwm], watermark 1:display plane 38, fbc lines 3,"
"cursor 6"},
{R, 1, "", 0x145d10, 0x2010040c, },
{W, 1, "", WM1_LP_ILK, 0x84302606, },
{R, 1, "", 0x145d10, 0x2010040c, },
{M, 1, "[drm:ironlake_check_srwm], watermark 2:display plane 145, fbc lines 3,"
"cursor 6"},
{R, 1, "", 0x145d10, 0x2010040c, },
{W, 1, "", WM2_LP_ILK, 0x90309106, },
{R, 1, "", 0x145d10, 0x2010040c, },
{M, 1, "[drm:ironlake_check_srwm], watermark 3:display plane 288, fbc lines 4,"
"cursor 10"},
{R, 1, "", 0x145d10, 0x2010040c, },
{W, 1, "", WM3_LP_ILK, 0xa041200a, },
{R, 1, "", _FDI_TXA_CTL, 0x00040000, },
{W, 1, "", _FDI_TXA_CTL, 0x00040000, },
{R, 1, "", _FDI_TXA_CTL, 0x00040000, },
{R, 1, "", _FDI_RXA_CTL, 0x00000040, },
{R, 1, "", _PIPEACONF, 0x00000050, },
{W, 1, "", _FDI_RXA_CTL, 0x00020040, },
{R, 1, "", _FDI_RXA_CTL, 0x00020040, 100},
{R, 1, "", SOUTH_CHICKEN1, 0x00000000, },
{W, 2, "", SOUTH_CHICKEN1, 0x00000000, },
{R, 1, "", SOUTH_CHICKEN1, 0x00000000, },
{R, 1, "", _FDI_TXA_CTL, 0x00040000, },
{W, 1, "", _FDI_TXA_CTL, 0x00040000, },
{R, 1, "", _FDI_RXA_CTL, 0x00020040, },
{R, 1, "", _PIPEACONF, 0x00000050, },
{W, 1, "", _FDI_RXA_CTL, 0x00020040, },
{R, 1, "", _FDI_RXA_CTL, 0x00020040, 100},
{W, 1, "", _LGC_PALETTE_A, 0x00000000, },
{W, 1, "", _LGC_PALETTE_A+0x4, 0x00010101, },
{W, 1, "", _LGC_PALETTE_A+0x8, 0x00020202, },
{W, 1, "", _LGC_PALETTE_A+0xc, 0x00030303, },
{W, 1, "", _LGC_PALETTE_A+0x10, 0x00040404, },
{W, 1, "", _LGC_PALETTE_A+0x14, 0x00050505, },
{W, 1, "", _LGC_PALETTE_A+0x18, 0x00060606, },
{W, 1, "", _LGC_PALETTE_A+0x1c, 0x00070707, },
{W, 1, "", _LGC_PALETTE_A+0x20, 0x00080808, },
{W, 1, "", _LGC_PALETTE_A+0x24, 0x00090909, },
{W, 1, "", _LGC_PALETTE_A+0x28, 0x000a0a0a, },
{W, 1, "", _LGC_PALETTE_A+0x2c, 0x000b0b0b, },
{W, 1, "", _LGC_PALETTE_A+0x30, 0x000c0c0c, },
{W, 1, "", _LGC_PALETTE_A+0x34, 0x000d0d0d, },
{W, 1, "", _LGC_PALETTE_A+0x38, 0x000e0e0e, },
{W, 1, "", _LGC_PALETTE_A+0x3c, 0x000f0f0f, },
{W, 1, "", _LGC_PALETTE_A+0x40, 0x00101010, },
{W, 1, "", _LGC_PALETTE_A+0x44, 0x00111111, },
{W, 1, "", _LGC_PALETTE_A+0x48, 0x00121212, },
{W, 1, "", _LGC_PALETTE_A+0x4c, 0x00131313, },
{W, 1, "", _LGC_PALETTE_A+0x50, 0x00141414, },
{W, 1, "", _LGC_PALETTE_A+0x54, 0x00151515, },
{W, 1, "", _LGC_PALETTE_A+0x58, 0x00161616, },
{W, 1, "", _LGC_PALETTE_A+0x5c, 0x00171717, },
{W, 1, "", _LGC_PALETTE_A+0x60, 0x00181818, },
{W, 1, "", _LGC_PALETTE_A+0x64, 0x00191919, },
{W, 1, "", _LGC_PALETTE_A+0x68, 0x001a1a1a, },
{W, 1, "", _LGC_PALETTE_A+0x6c, 0x001b1b1b, },
{W, 1, "", _LGC_PALETTE_A+0x70, 0x001c1c1c, },
{W, 1, "", _LGC_PALETTE_A+0x74, 0x001d1d1d, },
{W, 1, "", _LGC_PALETTE_A+0x78, 0x001e1e1e, },
{W, 1, "", _LGC_PALETTE_A+0x7c, 0x001f1f1f, },
{W, 1, "", 0x4a080, 0x00202020, },
{W, 1, "", 0x4a084, 0x00212121, },
{W, 1, "", 0x4a088, 0x00222222, },
{W, 1, "", 0x4a08c, 0x00232323, },
{W, 1, "", 0x4a090, 0x00242424, },
{W, 1, "", 0x4a094, 0x00252525, },
{W, 1, "", 0x4a098, 0x00262626, },
{W, 1, "", 0x4a09c, 0x00272727, },
{W, 1, "", 0x4a0a0, 0x00282828, },
{W, 1, "", 0x4a0a4, 0x00292929, },
{W, 1, "", 0x4a0a8, 0x002a2a2a, },
{W, 1, "", 0x4a0ac, 0x002b2b2b, },
{W, 1, "", 0x4a0b0, 0x002c2c2c, },
{W, 1, "", 0x4a0b4, 0x002d2d2d, },
{W, 1, "", 0x4a0b8, 0x002e2e2e, },
{W, 1, "", 0x4a0bc, 0x002f2f2f, },
{W, 1, "", 0x4a0c0, 0x00303030, },
{W, 1, "", 0x4a0c4, 0x00313131, },
{W, 1, "", 0x4a0c8, 0x00323232, },
{W, 1, "", 0x4a0cc, 0x00333333, },
{W, 1, "", 0x4a0d0, 0x00343434, },
{W, 1, "", 0x4a0d4, 0x00353535, },
{W, 1, "", 0x4a0d8, 0x00363636, },
{W, 1, "", 0x4a0dc, 0x00373737, },
{W, 1, "", 0x4a0e0, 0x00383838, },
{W, 1, "", 0x4a0e4, 0x00393939, },
{W, 1, "", 0x4a0e8, 0x003a3a3a, },
{W, 1, "", 0x4a0ec, 0x003b3b3b, },
{W, 1, "", 0x4a0f0, 0x003c3c3c, },
{W, 1, "", 0x4a0f4, 0x003d3d3d, },
{W, 1, "", 0x4a0f8, 0x003e3e3e, },
{W, 1, "", 0x4a0fc, 0x003f3f3f, },
{W, 1, "", 0x4a100, 0x00404040, },
{W, 1, "", 0x4a104, 0x00414141, },
{W, 1, "", 0x4a108, 0x00424242, },
{W, 1, "", 0x4a10c, 0x00434343, },
{W, 1, "", 0x4a110, 0x00444444, },
{W, 1, "", 0x4a114, 0x00454545, },
{W, 1, "", 0x4a118, 0x00464646, },
{W, 1, "", 0x4a11c, 0x00474747, },
{W, 1, "", 0x4a120, 0x00484848, },
{W, 1, "", 0x4a124, 0x00494949, },
{W, 1, "", 0x4a128, 0x004a4a4a, },
{W, 1, "", 0x4a12c, 0x004b4b4b, },
{W, 1, "", 0x4a130, 0x004c4c4c, },
{W, 1, "", 0x4a134, 0x004d4d4d, },
{W, 1, "", 0x4a138, 0x004e4e4e, },
{W, 1, "", 0x4a13c, 0x004f4f4f, },
{W, 1, "", 0x4a140, 0x00505050, },
{W, 1, "", 0x4a144, 0x00515151, },
{W, 1, "", 0x4a148, 0x00525252, },
{W, 1, "", 0x4a14c, 0x00535353, },
{W, 1, "", 0x4a150, 0x00545454, },
{W, 1, "", 0x4a154, 0x00555555, },
{W, 1, "", 0x4a158, 0x00565656, },
{W, 1, "", 0x4a15c, 0x00575757, },
{W, 1, "", 0x4a160, 0x00585858, },
{W, 1, "", 0x4a164, 0x00595959, },
{W, 1, "", 0x4a168, 0x005a5a5a, },
{W, 1, "", 0x4a16c, 0x005b5b5b, },
{W, 1, "", 0x4a170, 0x005c5c5c, },
{W, 1, "", 0x4a174, 0x005d5d5d, },
{W, 1, "", 0x4a178, 0x005e5e5e, },
{W, 1, "", 0x4a17c, 0x005f5f5f, },
{W, 1, "", 0x4a180, 0x00606060, },
{W, 1, "", 0x4a184, 0x00616161, },
{W, 1, "", 0x4a188, 0x00626262, },
{W, 1, "", 0x4a18c, 0x00636363, },
{W, 1, "", 0x4a190, 0x00646464, },
{W, 1, "", 0x4a194, 0x00656565, },
{W, 1, "", 0x4a198, 0x00666666, },
{W, 1, "", 0x4a19c, 0x00676767, },
{W, 1, "", 0x4a1a0, 0x00686868, },
{W, 1, "", 0x4a1a4, 0x00696969, },
{W, 1, "", 0x4a1a8, 0x006a6a6a, },
{W, 1, "", 0x4a1ac, 0x006b6b6b, },
{W, 1, "", 0x4a1b0, 0x006c6c6c, },
{W, 1, "", 0x4a1b4, 0x006d6d6d, },
{W, 1, "", 0x4a1b8, 0x006e6e6e, },
{W, 1, "", 0x4a1bc, 0x006f6f6f, },
{W, 1, "", 0x4a1c0, 0x00707070, },
{W, 1, "", 0x4a1c4, 0x00717171, },
{W, 1, "", 0x4a1c8, 0x00727272, },
{W, 1, "", 0x4a1cc, 0x00737373, },
{W, 1, "", 0x4a1d0, 0x00747474, },
{W, 1, "", 0x4a1d4, 0x00757575, },
{W, 1, "", 0x4a1d8, 0x00767676, },
{W, 1, "", 0x4a1dc, 0x00777777, },
{W, 1, "", 0x4a1e0, 0x00787878, },
{W, 1, "", 0x4a1e4, 0x00797979, },
{W, 1, "", 0x4a1e8, 0x007a7a7a, },
{W, 1, "", 0x4a1ec, 0x007b7b7b, },
{W, 1, "", 0x4a1f0, 0x007c7c7c, },
{W, 1, "", 0x4a1f4, 0x007d7d7d, },
{W, 1, "", 0x4a1f8, 0x007e7e7e, },
{W, 1, "", 0x4a1fc, 0x007f7f7f, },
{W, 1, "", 0x4a200, 0x00808080, },
{W, 1, "", 0x4a204, 0x00818181, },
{W, 1, "", 0x4a208, 0x00828282, },
{W, 1, "", 0x4a20c, 0x00838383, },
{W, 1, "", 0x4a210, 0x00848484, },
{W, 1, "", 0x4a214, 0x00858585, },
{W, 1, "", 0x4a218, 0x00868686, },
{W, 1, "", 0x4a21c, 0x00878787, },
{W, 1, "", 0x4a220, 0x00888888, },
{W, 1, "", 0x4a224, 0x00898989, },
{W, 1, "", 0x4a228, 0x008a8a8a, },
{W, 1, "", 0x4a22c, 0x008b8b8b, },
{W, 1, "", 0x4a230, 0x008c8c8c, },
{W, 1, "", 0x4a234, 0x008d8d8d, },
{W, 1, "", 0x4a238, 0x008e8e8e, },
{W, 1, "", 0x4a23c, 0x008f8f8f, },
{W, 1, "", 0x4a240, 0x00909090, },
{W, 1, "", 0x4a244, 0x00919191, },
{W, 1, "", 0x4a248, 0x00929292, },
{W, 1, "", 0x4a24c, 0x00939393, },
{W, 1, "", 0x4a250, 0x00949494, },
{W, 1, "", 0x4a254, 0x00959595, },
{W, 1, "", 0x4a258, 0x00969696, },
{W, 1, "", 0x4a25c, 0x00979797, },
{W, 1, "", 0x4a260, 0x00989898, },
{W, 1, "", 0x4a264, 0x00999999, },
{W, 1, "", 0x4a268, 0x009a9a9a, },
{W, 1, "", 0x4a26c, 0x009b9b9b, },
{W, 1, "", 0x4a270, 0x009c9c9c, },
{W, 1, "", 0x4a274, 0x009d9d9d, },
{W, 1, "", 0x4a278, 0x009e9e9e, },
{W, 1, "", 0x4a27c, 0x009f9f9f, },
{W, 1, "", 0x4a280, 0x00a0a0a0, },
{W, 1, "", 0x4a284, 0x00a1a1a1, },
{W, 1, "", 0x4a288, 0x00a2a2a2, },
{W, 1, "", 0x4a28c, 0x00a3a3a3, },
{W, 1, "", 0x4a290, 0x00a4a4a4, },
{W, 1, "", 0x4a294, 0x00a5a5a5, },
{W, 1, "", 0x4a298, 0x00a6a6a6, },
{W, 1, "", 0x4a29c, 0x00a7a7a7, },
{W, 1, "", 0x4a2a0, 0x00a8a8a8, },
{W, 1, "", 0x4a2a4, 0x00a9a9a9, },
{W, 1, "", 0x4a2a8, 0x00aaaaaa, },
{W, 1, "", 0x4a2ac, 0x00ababab, },
{W, 1, "", 0x4a2b0, 0x00acacac, },
{W, 1, "", 0x4a2b4, 0x00adadad, },
{W, 1, "", 0x4a2b8, 0x00aeaeae, },
{W, 1, "", 0x4a2bc, 0x00afafaf, },
{W, 1, "", 0x4a2c0, 0x00b0b0b0, },
{W, 1, "", 0x4a2c4, 0x00b1b1b1, },
{W, 1, "", 0x4a2c8, 0x00b2b2b2, },
{W, 1, "", 0x4a2cc, 0x00b3b3b3, },
{W, 1, "", 0x4a2d0, 0x00b4b4b4, },
{W, 1, "", 0x4a2d4, 0x00b5b5b5, },
{W, 1, "", 0x4a2d8, 0x00b6b6b6, },
{W, 1, "", 0x4a2dc, 0x00b7b7b7, },
{W, 1, "", 0x4a2e0, 0x00b8b8b8, },
{W, 1, "", 0x4a2e4, 0x00b9b9b9, },
{W, 1, "", 0x4a2e8, 0x00bababa, },
{W, 1, "", 0x4a2ec, 0x00bbbbbb, },
{W, 1, "", 0x4a2f0, 0x00bcbcbc, },
{W, 1, "", 0x4a2f4, 0x00bdbdbd, },
{W, 1, "", 0x4a2f8, 0x00bebebe, },
{W, 1, "", 0x4a2fc, 0x00bfbfbf, },
{W, 1, "", 0x4a300, 0x00c0c0c0, },
{W, 1, "", 0x4a304, 0x00c1c1c1, },
{W, 1, "", 0x4a308, 0x00c2c2c2, },
{W, 1, "", 0x4a30c, 0x00c3c3c3, },
{W, 1, "", 0x4a310, 0x00c4c4c4, },
{W, 1, "", 0x4a314, 0x00c5c5c5, },
{W, 1, "", 0x4a318, 0x00c6c6c6, },
{W, 1, "", 0x4a31c, 0x00c7c7c7, },
{W, 1, "", 0x4a320, 0x00c8c8c8, },
{W, 1, "", 0x4a324, 0x00c9c9c9, },
{W, 1, "", 0x4a328, 0x00cacaca, },
{W, 1, "", 0x4a32c, 0x00cbcbcb, },
{W, 1, "", 0x4a330, 0x00cccccc, },
{W, 1, "", 0x4a334, 0x00cdcdcd, },
{W, 1, "", 0x4a338, 0x00cecece, },
{W, 1, "", 0x4a33c, 0x00cfcfcf, },
{W, 1, "", 0x4a340, 0x00d0d0d0, },
{W, 1, "", 0x4a344, 0x00d1d1d1, },
{W, 1, "", 0x4a348, 0x00d2d2d2, },
{W, 1, "", 0x4a34c, 0x00d3d3d3, },
{W, 1, "", 0x4a350, 0x00d4d4d4, },
{W, 1, "", 0x4a354, 0x00d5d5d5, },
{W, 1, "", 0x4a358, 0x00d6d6d6, },
{W, 1, "", 0x4a35c, 0x00d7d7d7, },
{W, 1, "", 0x4a360, 0x00d8d8d8, },
{W, 1, "", 0x4a364, 0x00d9d9d9, },
{W, 1, "", 0x4a368, 0x00dadada, },
{W, 1, "", 0x4a36c, 0x00dbdbdb, },
{W, 1, "", 0x4a370, 0x00dcdcdc, },
{W, 1, "", 0x4a374, 0x00dddddd, },
{W, 1, "", 0x4a378, 0x00dedede, },
{W, 1, "", 0x4a37c, 0x00dfdfdf, },
{W, 1, "", 0x4a380, 0x00e0e0e0, },
{W, 1, "", 0x4a384, 0x00e1e1e1, },
{W, 1, "", 0x4a388, 0x00e2e2e2, },
{W, 1, "", 0x4a38c, 0x00e3e3e3, },
{W, 1, "", 0x4a390, 0x00e4e4e4, },
{W, 1, "", 0x4a394, 0x00e5e5e5, },
{W, 1, "", 0x4a398, 0x00e6e6e6, },
{W, 1, "", 0x4a39c, 0x00e7e7e7, },
{W, 1, "", 0x4a3a0, 0x00e8e8e8, },
{W, 1, "", 0x4a3a4, 0x00e9e9e9, },
{W, 1, "", 0x4a3a8, 0x00eaeaea, },
{W, 1, "", 0x4a3ac, 0x00ebebeb, },
{W, 1, "", 0x4a3b0, 0x00ececec, },
{W, 1, "", 0x4a3b4, 0x00ededed, },
{W, 1, "", 0x4a3b8, 0x00eeeeee, },
{W, 1, "", 0x4a3bc, 0x00efefef, },
{W, 1, "", 0x4a3c0, 0x00f0f0f0, },
{W, 1, "", 0x4a3c4, 0x00f1f1f1, },
{W, 1, "", 0x4a3c8, 0x00f2f2f2, },
{W, 1, "", 0x4a3cc, 0x00f3f3f3, },
{W, 1, "", 0x4a3d0, 0x00f4f4f4, },
{W, 1, "", 0x4a3d4, 0x00f5f5f5, },
{W, 1, "", 0x4a3d8, 0x00f6f6f6, },
{W, 1, "", 0x4a3dc, 0x00f7f7f7, },
{W, 1, "", 0x4a3e0, 0x00f8f8f8, },
{W, 1, "", 0x4a3e4, 0x00f9f9f9, },
{W, 1, "", 0x4a3e8, 0x00fafafa, },
{W, 1, "", 0x4a3ec, 0x00fbfbfb, },
{W, 1, "", 0x4a3f0, 0x00fcfcfc, },
{W, 1, "", 0x4a3f4, 0x00fdfdfd, },
{W, 1, "", 0x4a3f8, 0x00fefefe, },
{W, 1, "", 0x4a3fc, 0x00ffffff, },
{R, 1, "", _PIPEACONF, 0x00000050, },
{W, 1, "", _PIPEACONF, 0x80000050, },
{R, 1, "", _PIPEASTAT, 0x00000000, },
{W, 1, "", _PIPEASTAT, 0x00000002, },
{R, 4533, "", _PIPEASTAT, 0x00000000, },
{M, 1, "[drm:intel_wait_for_vblank], vblank wait timed out"},
{R, 1, "", _PIPEACONF, 0xc0000050, },
{R, 1, "", _DSPACNTR, 0x58004000, },
{W, 1, "", _DSPACNTR, 0xd8004000, },
{R, 1, "", _DSPAADDR, 0x00000000, },
{W, 1, "", _DSPAADDR, 0x00000000, },
{R, 1, "", _DSPASIZE+0xc, 0x00000000, },
{W, 1, "", _DSPASIZE+0xc, 0x00000000, },
{R, 1, "", _PIPEASTAT, 0x00000000, },
{W, 1, "", _PIPEASTAT, 0x00000002, },
{R, 4392, "", _PIPEASTAT, 0x00000000, },
{M, 1, "[drm:intel_wait_for_vblank], vblank wait timed out"},
{M, 1, "[drm:ironlake_edp_panel_vdd_on], Turn eDP VDD on"},
{R, 1, "", PCH_PP_CONTROL, 0xabcd0008, },
{M, 1, "[drm:ironlake_edp_panel_on], Turn eDP power on"},
{R, 1, "", PCH_PP_STATUS, 0x00000000, },
{M, 1, "[drm:ironlake_wait_panel_power_cycle], Wait for panel power cycle"},
{M, 1, "[drm:ironlake_wait_panel_status], R PCH_PP_CONTROL:abcd0008"},
{R, 2, "", PCH_PP_STATUS, 0x00000000, },
{R, 1, "", PCH_PP_CONTROL, 0xabcd0008, },
{W, 1, "", PCH_PP_CONTROL, 0xabcd000b, },
{R, 1, "", PCH_PP_CONTROL, 0xabcd000b, },
{M, 1, "[drm:ironlake_wait_panel_on], Wait for panel power on"},
{M, 1, "[drm:ironlake_wait_panel_status], R PCH_PP_CONTROL:abcd000b"},
{R, 4, "", PCH_PP_STATUS, 0x0000000a, },
{R, 16983, "", PCH_PP_STATUS, 0x9000000a, },
{R, 17839, "", PCH_PP_STATUS, 0x90000009, },
{R, 1, "", PCH_PP_STATUS, 0x80000008, },
//{V, 7,},
{M, 1, "[drm:ironlake_edp_panel_vdd_off], Turn eDP VDD off 1"},
{R, 2, "", PCH_PP_CONTROL, 0xabcd000b, },
{W, 1, "", PCH_PP_CONTROL, 0xabcd0003, },
{R, 1, "", PCH_PP_CONTROL, 0xabcd0003, },
{M, 1, "[drm:ironlake_panel_vdd_off_sync], R PCH_PP_CONTROL:abcd0003"},
{R, 1, "", PCH_PP_STATUS, 0x80000008, },
{W, 1, "", 0x64000, 0x8e1c4104, },
{R, 1, "", 0x64000, 0x8e1c4104, },
{R, 2, "", PCH_PP_STATUS, 0x80000008, },
{R, 1, "", 0x64000, 0x8cdc4104, },
{M, 1, "[drm:intel_dp_link_down], "},
{W, 1, "", 0x64000, 0x8e1c0004, },
{R, 1, "", 0x64000, 0x8e1c0004, 100},
{W, 1, "", 0x64000, 0x8e1c0204, },
{R, 1, "", 0x64000, 0x8e1c0204, },
{W, 1, "", 0x64000, 0x0e1c0304, },
{R, 2, "", 0x64000, 0x0e1c0304, },
{R, 2, "", PCH_PP_STATUS, 0x80000008, },
{R, 1, "", DPA_AUX_CH_CTL, 0x007500c8, },
{W, 1, "", DPA_AUX_CH_DATA1, 0x80010008, },
{W, 1, "", DPA_AUX_CH_DATA2, 0x0a840000, },
{W, 1, "", DPA_AUX_CH_DATA3, 0x00000000, },
{W, 1, "", DPA_AUX_CH_DATA4, 0x01000000, },
{W, 1, "", DPA_AUX_CH_CTL, 0xd2d500c8, },
{R, 3, "", DPA_AUX_CH_CTL, 0x807500c8, 100},
{R, 1, "", DPA_AUX_CH_CTL, 0x401500c8, },
{W, 1, "", DPA_AUX_CH_CTL, 0x521500c8, },
{R, 1, "", DPA_AUX_CH_DATA1, 0x00000000, },
{W, 1, "", 0x64000, 0x891c4004, },
{R, 1, "", 0x64000, 0x891c4004, },
{R, 2, "", PCH_PP_STATUS, 0x80000008, },
{R, 1, "", DPA_AUX_CH_CTL, 0x001500c8, },
{W, 1, "", DPA_AUX_CH_DATA1, 0x80010200, },
{W, 1, "", DPA_AUX_CH_DATA2, 0x21000000, },
{W, 1, "", DPA_AUX_CH_CTL, 0xd25500c8, },
{R, 2, "", DPA_AUX_CH_CTL, 0x801500c8, 100},
{R, 1, "", DPA_AUX_CH_CTL, 0x401500c8, },
{W, 1, "", DPA_AUX_CH_CTL, 0x521500c8, },
{R, 1, "", DPA_AUX_CH_DATA1, 0x00000000, },
{R, 2, "", PCH_PP_STATUS, 0x80000008, },
{R, 1, "", DPA_AUX_CH_CTL, 0x001500c8, },
{W, 1, "", DPA_AUX_CH_DATA1, 0x80010303, },
{W, 1, "", DPA_AUX_CH_DATA2, 0x00000000, },
{W, 1, "", DPA_AUX_CH_CTL, 0xd28500c8, },
{R, 3, "", DPA_AUX_CH_CTL, 0x801500c8, 100},
{R, 1, "", DPA_AUX_CH_CTL, 0x401500c8, },
{W, 1, "", DPA_AUX_CH_CTL, 0x521500c8, },
{R, 1, "", DPA_AUX_CH_DATA1, 0x00000000, 100},
{R, 2, "", PCH_PP_STATUS, 0x80000008, },
{R, 1, "", DPA_AUX_CH_CTL, 0x001500c8, },
{W, 1, "", DPA_AUX_CH_DATA1, 0x90020205, },
{W, 1, "", DPA_AUX_CH_CTL, 0xd24500c8, },
{R, 2, "", DPA_AUX_CH_CTL, 0x801500c8, 100},
{R, 1, "", DPA_AUX_CH_CTL, 0x804500c8, 100},
{R, 1, "", DPA_AUX_CH_CTL, 0x407500c8, },
{W, 1, "", DPA_AUX_CH_CTL, 0x527500c8, },
{R, 1, "", DPA_AUX_CH_DATA1, 0x00111180, },
{R, 1, "", DPA_AUX_CH_DATA2, 0x02000000, },
{M, 1, "[drm:intel_dp_start_link_train], clock recovery OK"},
{W, 1, "", 0x64000, 0x891c4104, },
{R, 1, "", 0x64000, 0x891c4104, },
{R, 2, "", PCH_PP_STATUS, 0x80000008, },
{R, 1, "", DPA_AUX_CH_CTL, 0x007500c8, },
{W, 1, "", DPA_AUX_CH_DATA1, 0x80010200, },
{W, 1, "", DPA_AUX_CH_DATA2, 0x22000000, },
{W, 1, "", DPA_AUX_CH_CTL, 0xd25500c8, },
{R, 2, "", DPA_AUX_CH_CTL, 0x807500c8, 100},
{R, 1, "", DPA_AUX_CH_CTL, 0x401500c8, },
{W, 1, "", DPA_AUX_CH_CTL, 0x521500c8, },
{R, 1, "", DPA_AUX_CH_DATA1, 0x00000000, },
{R, 2, "", PCH_PP_STATUS, 0x80000008, },
{R, 1, "", DPA_AUX_CH_CTL, 0x001500c8, },
{W, 1, "", DPA_AUX_CH_DATA1, 0x80010303, },
{W, 1, "", DPA_AUX_CH_DATA2, 0x00000000, },
{W, 1, "", DPA_AUX_CH_CTL, 0xd28500c8, },
{R, 2, "", DPA_AUX_CH_CTL, 0x801500c8, 100},
{R, 1, "", DPA_AUX_CH_CTL, 0x800500c8, 100},
{R, 1, "", DPA_AUX_CH_CTL, 0x401500c8, },
{W, 1, "", DPA_AUX_CH_CTL, 0x521500c8, },
{R, 1, "", DPA_AUX_CH_DATA1, 0x00000000, 400},
{R, 2, "", PCH_PP_STATUS, 0x80000008, },
{R, 1, "", DPA_AUX_CH_CTL, 0x001500c8, },
{W, 1, "", DPA_AUX_CH_DATA1, 0x90020205, },
{W, 1, "", DPA_AUX_CH_CTL, 0xd24500c8, },
{R, 2, "", DPA_AUX_CH_CTL, 0x801500c8, 100},
{R, 1, "", DPA_AUX_CH_CTL, 0x804500c8, 100},
{R, 1, "", DPA_AUX_CH_CTL, 0x407500c8, },
{W, 1, "", DPA_AUX_CH_CTL, 0x527500c8, },
{R, 1, "", DPA_AUX_CH_DATA1, 0x00777781, },
{R, 1, "", DPA_AUX_CH_DATA2, 0x02000000, },
{W, 1, "", 0x64000, 0x891c4304, },
{R, 1, "", 0x64000, 0x891c4304, },
{R, 2, "", PCH_PP_STATUS, 0x80000008, },
{R, 1, "", DPA_AUX_CH_CTL, 0x007500c8, },
{W, 1, "", DPA_AUX_CH_DATA1, 0x80010200, },
{W, 1, "", DPA_AUX_CH_DATA2, 0x00000000, },
{W, 1, "", DPA_AUX_CH_CTL, 0xd25500c8, },
{R, 2, "", DPA_AUX_CH_CTL, 0x807500c8, 100},
{R, 1, "", DPA_AUX_CH_CTL, 0x401500c8, },
{W, 1, "", DPA_AUX_CH_CTL, 0x521500c8, },
{R, 1, "", DPA_AUX_CH_DATA1, 0x00000000, },
{M, 1, "[drm:ironlake_edp_backlight_on], "},
{R, 1, "", PCH_PP_CONTROL, 0xabcd0003, },
{W, 1, "", PCH_PP_CONTROL, 0xabcd0007, },
{R, 1, "", PCH_PP_CONTROL, 0xabcd0007, },
{R, 1, "", _PIPEADSL, 0x00000633, 500},
{R, 1, "", _PIPEADSL, 0x00000652, },
{R, 1, "", _PIPEASTAT, 0x00000000, },
{W, 1, "", _PIPEASTAT, 0x00000002, },
{R, 5085, "", _PIPEASTAT, 0x00000000, },
{M, 1, "[drm:intel_wait_for_vblank], vblank wait timed out"},
{M, 1, "[drm:intel_dp_mode_fixup], Display port link bw 0a lane count 4"
"clock 270000"},
{M, 1, "[drm:drm_crtc_helper_set_mode], [CRTC:3]"},
{0,},
};

60
src/mainboard/google/link/i915io.h Normal file
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/*
* This file is part of the coreboot project.
*
* Copyright (C) 2012 Google Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
#include "i915_reg.h"
/* One-letter commands for code not meant to be ready for humans.
* The code was generated by a set of programs/scripts.
* M print out a kernel message
* R read a register. We do these mainly to ensure that if hardware wanted
* the register read, it was read; also, in debug, we can see what was expected
* and what was found. This has proven *very* useful to get this debugged.
* The udelay, if non-zero, will make sure there is a
* udelay() call with the value.
* The count is from the kernel and tells us how many times this read was done.
* Also useful for debugging and the state
* machine uses the info to drive a poll.
* W Write a register
* V set verbosity. It's a bit mask.
* 0 -> nothing
* 1 -> print kernel messages
* 2 -> print IO ops
* 4 -> print the number of times we spin on a register in a poll
* 8 -> restore whatever the previous verbosity level was
* (only one deep stack)
*
* Again, this is not really meant for human consumption. There is not a poll
* operator as such because, sometimes, there is a read/write/read where the
* second read is a poll, and this chipset is so touchy I'm reluctant to move
* things around and/or delete too many reads.
*/
#define M 1
#define R 2
#define W 3
#define V 4
#define I 8
struct iodef {
unsigned char op;
unsigned int count;
const char *msg;
unsigned long addr;
unsigned long data;
unsigned long udelay;
};

356
src/mainboard/google/link/mainboard.c Normal file
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/*
* This file is part of the coreboot project.
*
* Copyright (C) 2007-2009 coresystems GmbH
* Copyright (C) 2011 Google Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
#include <types.h>
#include <string.h>
#include <device/device.h>
#include <device/device.h>
#include <device/pci_def.h>
#include <device/pci_ops.h>
#include <console/console.h>
#if defined(CONFIG_PCI_OPTION_ROM_RUN_YABEL) && CONFIG_PCI_OPTION_ROM_RUN_YABEL
#include <x86emu/x86emu.h>
#endif
#include <pc80/mc146818rtc.h>
#include <arch/acpi.h>
#include <arch/io.h>
#include <arch/interrupt.h>
#include <arch/coreboot_tables.h>
#include "hda_verb.h"
#include "onboard.h"
#include "ec.h"
#include <southbridge/intel/bd82x6x/pch.h>
#include <smbios.h>
#include <device/pci.h>
#include <ec/google/chromeec/ec.h>
/* placeholder for evenual link post. Not sure what we'll
* do but it will look nice
*/
void mainboard_post(u8 value)
{
/*
* What you DO NOT want to do: push every post to the EC backlight.
* it seems cute but in practice it looks like a hardware failure.
* I'm leaving this here so we don't make this mistake again later.
* And it seems to break the SMP startup.
* google_chromeec_post(value);
*/
}
void mainboard_suspend_resume(void)
{
/* Call SMM finalize() handlers before resume */
outb(0xcb, 0xb2);
}
#if defined(CONFIG_PCI_OPTION_ROM_RUN_REALMODE) && CONFIG_PCI_OPTION_ROM_RUN_REALMODE
static int int15_handler(struct eregs *regs)
{
int res=-1;
printk(BIOS_DEBUG, "%s: INT15 function %04x!\n",
__func__, regs->eax & 0xffff);
switch(regs->eax & 0xffff) {
case 0x5f34:
/*
* Set Panel Fitting Hook:
* bit 2 = Graphics Stretching
* bit 1 = Text Stretching
* bit 0 = Centering (do not set with bit1 or bit2)
* 0 = video bios default
*/
regs->eax &= 0xffff0000;
regs->eax |= 0x005f;
regs->ecx &= 0xffffff00;
regs->ecx |= 0x00; /* Use video bios default */
res = 0;
break;
case 0x5f35:
/*
* Boot Display Device Hook:
* bit 0 = CRT
* bit 1 = TV (eDP)
* bit 2 = EFP
* bit 3 = LFP
* bit 4 = CRT2
* bit 5 = TV2 (eDP)
* bit 6 = EFP2
* bit 7 = LFP2
*/
regs->eax &= 0xffff0000;
regs->eax |= 0x005f;
regs->ecx &= 0xffff0000;
regs->ecx |= 0x0000; /* Use video bios default */
res = 0;
break;
case 0x5f51:
/*
* Hook to select active LFP configuration:
* 00h = No LVDS, VBIOS does not enable LVDS
* 01h = Int-LVDS, LFP driven by integrated LVDS decoder
* 02h = SVDO-LVDS, LFP driven by SVDO decoder
* 03h = eDP, LFP Driven by Int-DisplayPort encoder
*/
regs->eax &= 0xffff0000;
regs->eax |= 0x005f;
regs->ecx &= 0xffff0000;
regs->ecx |= 0x0003; /* eDP */
res = 0;
break;
case 0x5f70:
switch ((regs->ecx >> 8) & 0xff) {
case 0:
/* Get Mux */
regs->eax &= 0xffff0000;
regs->eax |= 0x005f;
regs->ecx &= 0xffff0000;
regs->ecx |= 0x0000;
res = 0;
break;
case 1:
/* Set Mux */
regs->eax &= 0xffff0000;
regs->eax |= 0x005f;
regs->ecx &= 0xffff0000;
regs->ecx |= 0x0000;
res = 0;
break;
case 2:
/* Get SG/Non-SG mode */
regs->eax &= 0xffff0000;
regs->eax |= 0x005f;
regs->ecx &= 0xffff0000;
regs->ecx |= 0x0000;
res = 0;
break;
default:
/* Interrupt was not handled */
printk(BIOS_DEBUG, "Unknown INT15 5f70 function: 0x%02x\n",
((regs->ecx >> 8) & 0xff));
return 0;
}
break;
case 0x5fac:
res = 0;
break;
default:
printk(BIOS_DEBUG, "Unknown INT15 function %04x!\n",
regs->eax & 0xffff);
break;
}
return res;
}
#endif
#if defined(CONFIG_PCI_OPTION_ROM_RUN_YABEL) && CONFIG_PCI_OPTION_ROM_RUN_YABEL
static int int15_handler(void)
{
printk(BIOS_DEBUG, "%s: AX=%04x BX=%04x CX=%04x DX=%04x\n",
__func__, M.x86.R_AX, M.x86.R_BX, M.x86.R_CX, M.x86.R_DX);
switch (M.x86.R_AX) {
case 0x5f34:
/*
* Set Panel Fitting Hook:
* bit 2 = Graphics Stretching
* bit 1 = Text Stretching
* bit 0 = Centering (do not set with bit1 or bit2)
*/
M.x86.R_AX = 0x005f;
M.x86.R_CX = 0x00;
break;
case 0x5f35:
/*
* Boot Display Device Hook:
* bit 0 = CRT
* bit 1 = TV (eDP)
* bit 2 = EFP
* bit 3 = LFP
* bit 4 = CRT2
* bit 5 = TV2 (eDP)
* bit 6 = EFP2
* bit 7 = LFP2
*/
M.x86.R_AX = 0x005f;
M.x86.R_CX = 0x0000; /* Use video bios default */
break;
case 0x5f51:
/*
* Hook to select active LFP configuration:
* 00h = No LVDS, VBIOS does not enable LVDS
* 01h = Int-LVDS, LFP driven by integrated LVDS decoder
* 02h = SVDO-LVDS, LFP driven by SVDO decoder
* 03h = eDP, LFP Driven by Int-DisplayPort encoder
*/
M.x86.R_AX = 0x005f;
M.x86.R_CX = 3; /* eDP */
break;
case 0x5f70:
switch (M.x86.R_CH) {
case 0:
/* Get Mux */
M.x86.R_AX = 0x005f;
M.x86.R_CL = 0;
break;
case 1:
/* Set Mux */
M.x86.R_AX = 0x005f;
M.x86.R_CX = 0;
break;
case 2:
/* Get SG/Non-SG mode */
M.x86.R_AX = 0x005f;
M.x86.R_CX = 0;
break;
default:
/* Interrupt was not handled */
printk(BIOS_DEBUG, "Unknown INT15 5f70 function: 0x%02x\n",
M.x86.R_CH);
return 0;
}
break;
case 0x5fac:
break;
default:
/* Interrupt was not handled */
printk(BIOS_DEBUG, "Unknown INT15 function: 0x%04x\n",
M.x86.R_AX);
return 0;
}
/* Interrupt handled */
return 1;
}
#endif
#if CONFIG_PCI_OPTION_ROM_RUN_YABEL || CONFIG_PCI_OPTION_ROM_RUN_REALMODE
static void int15_install(void)
{
#if CONFIG_PCI_OPTION_ROM_RUN_YABEL
typedef int (* yabel_handleIntFunc)(void);
extern yabel_handleIntFunc yabel_intFuncArray[256];
yabel_intFuncArray[0x15] = int15_handler;
#endif
#ifdef CONFIG_PCI_OPTION_ROM_RUN_REALMODE
mainboard_interrupt_handlers(0x15, &int15_handler);
#endif
}
#endif
/* Audio Setup */
extern const u32 * cim_verb_data;
extern u32 cim_verb_data_size;
extern const u32 * pc_beep_verbs;
extern u32 pc_beep_verbs_size;
static void verb_setup(void)
{
cim_verb_data = mainboard_cim_verb_data;
cim_verb_data_size = sizeof(mainboard_cim_verb_data);
pc_beep_verbs = mainboard_pc_beep_verbs;
pc_beep_verbs_size = mainboard_pc_beep_verbs_size;
}
static void mainboard_init(device_t dev)
{
/* Initialize the Embedded Controller */
link_ec_init();
if (google_chromeec_get_board_version() == 0) {
/* If running on proto1 - enable reversion of gpio11. */
u32 gpio_inv;
u16 gpio_base = pci_read_config16
(dev_find_slot(0, PCI_DEVFN(0x1f, 0)), GPIO_BASE) &
0xfffc;
u16 gpio_inv_addr = gpio_base + GPI_INV;
gpio_inv = inl(gpio_inv_addr);
outl(gpio_inv | (1 << 11), gpio_inv_addr);
}
}
static int link_smbios_type41(int *handle, unsigned long *current,
const char *name, u8 irq, u8 addr)
{
struct smbios_type41 *t = (struct smbios_type41 *)*current;
int len = sizeof(struct smbios_type41);
memset(t, 0, sizeof(struct smbios_type41));
t->type = SMBIOS_ONBOARD_DEVICES_EXTENDED_INFORMATION;
t->handle = *handle;
t->length = len - 2;
t->reference_designation = smbios_add_string(t->eos, name);
t->device_type = SMBIOS_DEVICE_TYPE_OTHER;
t->device_status = 1;
t->device_type_instance = irq;
t->segment_group_number = 0;
t->bus_number = addr;
t->function_number = 0;
t->device_number = 0;
len = t->length + smbios_string_table_len(t->eos);
*current += len;
*handle += 1;
return len;
}
static int link_onboard_smbios_data(device_t dev, int *handle,
unsigned long *current)
{
int len = 0;
len += link_smbios_type41(handle, current,
LINK_LIGHTSENSOR_NAME,
LINK_LIGHTSENSOR_IRQ,
LINK_LIGHTSENSOR_I2C_ADDR);
len += link_smbios_type41(handle, current,
LINK_TRACKPAD_NAME,
LINK_TRACKPAD_IRQ,
LINK_TRACKPAD_I2C_ADDR);
len += link_smbios_type41(handle, current,
LINK_TOUCHSCREEN_NAME,
LINK_TOUCHSCREEN_IRQ,
LINK_TOUCHSCREEN_I2C_ADDR);
return len;
}
// mainboard_enable is executed as first thing after
// enumerate_buses().
static void mainboard_enable(device_t dev)
{
dev->ops->init = mainboard_init;
dev->ops->get_smbios_data = link_onboard_smbios_data;
#if CONFIG_PCI_OPTION_ROM_RUN_YABEL || CONFIG_PCI_OPTION_ROM_RUN_REALMODE
/* Install custom int15 handler for VGA OPROM */
int15_install();
#endif
verb_setup();
}
struct chip_operations mainboard_ops = {
CHIP_NAME("Google Link Chromebook")
.enable_dev = mainboard_enable,
};

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src/mainboard/google/link/mainboard_smi.c Normal file
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/*
* This file is part of the coreboot project.
*
* Copyright (C) 2008-2009 coresystems GmbH
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
#include <arch/io.h>
#include <arch/romcc_io.h>
#include <console/console.h>
#include <cpu/x86/smm.h>
#include <southbridge/intel/bd82x6x/nvs.h>
#include <southbridge/intel/bd82x6x/pch.h>
#include <southbridge/intel/bd82x6x/me.h>
#include <northbridge/intel/sandybridge/sandybridge.h>
#include <cpu/intel/model_206ax/model_206ax.h>
#include <elog.h>
/* Include romstage serial for SIO helper functions */
#include <superio/ite/it8772f/early_serial.c>
/* Include EC functions */
#include <ec/google/chromeec/ec.h>
#include "ec.h"
int mainboard_io_trap_handler(int smif)
{
switch (smif) {
case 0x99:
printk(BIOS_DEBUG, "Sample\n");
smm_get_gnvs()->smif = 0;
break;
default:
return 0;
}
/* On success, the IO Trap Handler returns 0
* On failure, the IO Trap Handler returns a value != 0
*
* For now, we force the return value to 0 and log all traps to
* see what's going on.
*/
//gnvs->smif = 0;
return 1;
}
static u8 mainboard_smi_ec(void)
{
u8 cmd = google_chromeec_get_event();
u32 pm1_cnt;
#if CONFIG_ELOG_GSMI
/* Log this event */
if (cmd)
elog_add_event_byte(ELOG_TYPE_EC_EVENT, cmd);
#endif
switch (cmd) {
case EC_HOST_EVENT_LID_CLOSED:
printk(BIOS_DEBUG, "LID CLOSED, SHUTDOWN\n");
/* Go to S5 */
pm1_cnt = inl(smm_get_pmbase() + PM1_CNT);
pm1_cnt |= (0xf << 10);
outl(pm1_cnt, smm_get_pmbase() + PM1_CNT);
break;
}
return cmd;
}
void mainboard_smi_gpi(u16 gpi_sts)
{
if (gpi_sts & (1 << EC_SMI_GPI)) {
/* Process all pending events */
while (mainboard_smi_ec() != 0);
}
}
void mainboard_smi_sleep(u8 slp_typ)
{
/* Disable USB charging if required */
switch (slp_typ) {
case 3:
if (smm_get_gnvs()->s3u0 == 0)
google_chromeec_set_usb_charge_mode(
0, USB_CHARGE_MODE_DISABLED);
if (smm_get_gnvs()->s3u1 == 0)
google_chromeec_set_usb_charge_mode(
1, USB_CHARGE_MODE_DISABLED);
break;
case 5:
if (smm_get_gnvs()->s5u0 == 0)
google_chromeec_set_usb_charge_mode(
0, USB_CHARGE_MODE_DISABLED);
if (smm_get_gnvs()->s5u1 == 0)
google_chromeec_set_usb_charge_mode(
1, USB_CHARGE_MODE_DISABLED);
break;
}
/* Disable SCI and SMI events */
google_chromeec_set_smi_mask(0);
google_chromeec_set_sci_mask(0);
/* Clear pending events that may trigger immediate wake */
while (google_chromeec_get_event() != 0);
/* Enable wake events */
google_chromeec_set_wake_mask(LINK_EC_S3_WAKE_EVENTS);
}
#define APMC_FINALIZE 0xcb
#define APMC_ACPI_EN 0xe1
#define APMC_ACPI_DIS 0x1e
static int mainboard_finalized = 0;
int mainboard_smi_apmc(u8 apmc)
{
switch (apmc) {
case APMC_FINALIZE:
if (mainboard_finalized) {
printk(BIOS_DEBUG, "SMI#: Already finalized\n");
return 0;
}
intel_me_finalize_smm();
intel_pch_finalize_smm();
intel_sandybridge_finalize_smm();
intel_model_206ax_finalize_smm();
mainboard_finalized = 1;
break;
case APMC_ACPI_EN:
google_chromeec_set_smi_mask(0);
/* Clear all pending events */
while (google_chromeec_get_event() != 0);
google_chromeec_set_sci_mask(LINK_EC_SCI_EVENTS);
break;
case APMC_ACPI_DIS:
google_chromeec_set_sci_mask(0);
/* Clear all pending events */
while (google_chromeec_get_event() != 0);
google_chromeec_set_smi_mask(LINK_EC_SMI_EVENTS);;
break;
}
return 0;
}

32
src/mainboard/google/link/micron_4Gb_1600_1.35v_x16.spd.hex Normal file
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@ -0,0 +1,32 @@
92 11 0b 03 04 19 02 02
03 11 01 08 0a 00 fe 00
69 78 69 3c 69 11 18 81
20 08 3c 3c 01 40 83 05
00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00
00 00 00 00 0f 01 02 00
00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00
00 00 00 00 00 80 2c 00
00 00 00 00 00 00 ad 75
34 4b 54 46 32 35 36 36
34 48 5a 2d 31 47 36 45
31 20 45 31 80 2c 00 00
00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00
ff ff ff ff ff ff ff ff
ff ff ff ff ff ff ff ff
ff ff ff ff ff ff ff ff
ff ff ff ff ff ff ff ff
ff ff ff ff ff ff ff ff
ff ff ff ff ff ff ff ff
ff ff ff ff ff ff ff ff
ff ff ff ff ff ff ff ff
ff ff ff ff ff ff ff ff
ff ff ff ff ff ff ff ff

37
src/mainboard/google/link/onboard.h Normal file
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/*
* This file is part of the coreboot project.
*
* Copyright (C) 2011 Google Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
#ifndef LINK_ONBOARD_H
#define LINK_ONBOARD_H
#include <arch/smp/mpspec.h>
#define LINK_LIGHTSENSOR_NAME "lightsensor"
#define LINK_LIGHTSENSOR_I2C_ADDR 0x44
#define LINK_LIGHTSENSOR_IRQ 0
#define LINK_TRACKPAD_NAME "trackpad"
#define LINK_TRACKPAD_I2C_ADDR 0x4b
#define LINK_TRACKPAD_IRQ 20
#define LINK_TOUCHSCREEN_NAME "touchscreen"
#define LINK_TOUCHSCREEN_I2C_ADDR 0x4a
#define LINK_TOUCHSCREEN_IRQ 22
#endif

350
src/mainboard/google/link/romstage.c Normal file
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/*
* This file is part of the coreboot project.
*
* Copyright (C) 2007-2010 coresystems GmbH
* Copyright (C) 2011 Google Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
#include <stdint.h>
#include <string.h>
#include <lib.h>
#include <timestamp.h>
#include <arch/byteorder.h>
#include <arch/io.h>
#include <arch/romcc_io.h>
#include <device/pci.h>
#include <device/pci_def.h>
#include <device/pnp_def.h>
#include <cpu/x86/lapic.h>
#include <pc80/mc146818rtc.h>
#include <cbmem.h>
#include <console/console.h>
#include "northbridge/intel/sandybridge/sandybridge.h"
#include "northbridge/intel/sandybridge/raminit.h"
#include "southbridge/intel/bd82x6x/pch.h"
#include "southbridge/intel/bd82x6x/gpio.h"
#include "ec/google/chromeec/ec.h"
#include <arch/cpu.h>
#include <cpu/x86/bist.h>
#include <cpu/x86/msr.h>
#include "gpio.h"
#if CONFIG_CHROMEOS
#include <vendorcode/google/chromeos/chromeos.h>
#endif
#include <cbfs.h>
#include <southbridge/intel/bd82x6x/chip.h>
static void pch_enable_lpc(void)
{
const struct device *lpc;
const struct southbridge_intel_bd82x6x_config *config = NULL;
lpc = dev_find_slot(0, PCI_DEVFN(0x1f, 0));
if (!lpc)
return;
if (lpc->chip_info)
config = lpc->chip_info;
if (!config)
return;
/* Set COM1/COM2 decode range */
pci_write_config16(PCH_LPC_DEV, LPC_IO_DEC, 0x0010);
/* Enable PS/2 Keyboard/Mouse, EC areas and COM1 */
pci_write_config16(PCH_LPC_DEV, LPC_EN, KBC_LPC_EN | MC_LPC_EN | \
GAMEL_LPC_EN | COMA_LPC_EN);
pci_write_config32(PCH_LPC_DEV, LPC_GEN1_DEC, config->gen1_dec);
pci_write_config32(PCH_LPC_DEV, LPC_GEN2_DEC, config->gen2_dec);
pci_write_config32(PCH_LPC_DEV, LPC_GEN3_DEC, config->gen3_dec);
pci_write_config32(PCH_LPC_DEV, LPC_GEN4_DEC, config->gen4_dec);
}
static void rcba_config(void)
{
u32 reg32;
/*
* GFX INTA -> PIRQA (MSI)
* D28IP_P3IP WLAN INTA -> PIRQB
* D29IP_E1P EHCI1 INTA -> PIRQD
* D26IP_E2P EHCI2 INTA -> PIRQF
* D31IP_SIP SATA INTA -> PIRQF (MSI)
* D31IP_SMIP SMBUS INTB -> PIRQH
* D31IP_TTIP THRT INTC -> PIRQA
* D27IP_ZIP HDA INTA -> PIRQA (MSI)
*
* TRACKPAD -> PIRQE (Edge Triggered)
* TOUCHSCREEN -> PIRQG (Edge Triggered)
*/
/* Device interrupt pin register (board specific) */
RCBA32(D31IP) = (INTC << D31IP_TTIP) | (NOINT << D31IP_SIP2) |
(INTB << D31IP_SMIP) | (INTA << D31IP_SIP);
RCBA32(D30IP) = (NOINT << D30IP_PIP);
RCBA32(D29IP) = (INTA << D29IP_E1P);
RCBA32(D28IP) = (INTA << D28IP_P3IP);
RCBA32(D27IP) = (INTA << D27IP_ZIP);
RCBA32(D26IP) = (INTA << D26IP_E2P);
RCBA32(D25IP) = (NOINT << D25IP_LIP);
RCBA32(D22IP) = (NOINT << D22IP_MEI1IP);
/* Device interrupt route registers */
DIR_ROUTE(D31IR, PIRQB, PIRQH, PIRQA, PIRQC);
DIR_ROUTE(D29IR, PIRQD, PIRQE, PIRQF, PIRQG);
DIR_ROUTE(D28IR, PIRQB, PIRQC, PIRQD, PIRQE);
DIR_ROUTE(D27IR, PIRQA, PIRQH, PIRQA, PIRQB);
DIR_ROUTE(D26IR, PIRQF, PIRQE, PIRQG, PIRQH);
DIR_ROUTE(D25IR, PIRQA, PIRQB, PIRQC, PIRQD);
DIR_ROUTE(D22IR, PIRQA, PIRQB, PIRQC, PIRQD);
/* Enable IOAPIC (generic) */
RCBA16(OIC) = 0x0100;
/* PCH BWG says to read back the IOAPIC enable register */
(void) RCBA16(OIC);
/* Disable unused devices (board specific) */
reg32 = RCBA32(FD);
reg32 |= PCH_DISABLE_ALWAYS;
RCBA32(FD) = reg32;
}
static void copy_spd(struct pei_data *peid)
{
const int gpio_vector[] = {41, 42, 43, 10, -1};
struct cbfs_file *spd_file;
int spd_index = get_gpios(gpio_vector);
printk(BIOS_DEBUG, "spd index %d\n", spd_index);
spd_file = cbfs_get_file(CBFS_DEFAULT_MEDIA, "spd.bin");
if (!spd_file)
die("SPD data not found.");
if (ntohl(spd_file->len) < ((spd_index + 1) * sizeof(peid->spd_data[0]))) {
printk(BIOS_ERR, "spd index override to 0 - old hardware?\n");
spd_index = 0;
}
if (spd_file->len < sizeof(peid->spd_data[0]))
die("Missing SPD data.");
memcpy(peid->spd_data[0],
((char*)CBFS_SUBHEADER(spd_file)) +
spd_index * sizeof(peid->spd_data[0]),
sizeof(peid->spd_data[0]));
}
void main(unsigned long bist)
{
int boot_mode = 0;
int cbmem_was_initted;
u32 pm1_cnt;
u16 pm1_sts;
#if CONFIG_COLLECT_TIMESTAMPS
tsc_t start_romstage_time;
tsc_t before_dram_time;
tsc_t after_dram_time;
tsc_t base_time = {
.lo = pci_read_config32(PCI_DEV(0, 0x00, 0), 0xdc),
.hi = pci_read_config32(PCI_DEV(0, 0x1f, 2), 0xd0)
};
#endif
struct pei_data pei_data = {
pei_version: PEI_VERSION,
mchbar: DEFAULT_MCHBAR,
dmibar: DEFAULT_DMIBAR,
epbar: DEFAULT_EPBAR,
pciexbar: CONFIG_MMCONF_BASE_ADDRESS,
smbusbar: SMBUS_IO_BASE,
wdbbar: 0x4000000,
wdbsize: 0x1000,
hpet_address: CONFIG_HPET_ADDRESS,
rcba: DEFAULT_RCBABASE,
pmbase: DEFAULT_PMBASE,
gpiobase: DEFAULT_GPIOBASE,
thermalbase: 0xfed08000,
system_type: 0, // 0 Mobile, 1 Desktop/Server
tseg_size: CONFIG_SMM_TSEG_SIZE,
ts_addresses: { 0x00, 0x00, 0x00, 0x00 },
ec_present: 1,
ddr3lv_support: 1,
// 0 = leave channel enabled
// 1 = disable dimm 0 on channel
// 2 = disable dimm 1 on channel
// 3 = disable dimm 0+1 on channel
dimm_channel0_disabled: 2,
dimm_channel1_disabled: 2,
max_ddr3_freq: 1600,
usb_port_config: {
/* Empty and onboard Ports 0-7, set to un-used pin OC3 */
{ 0, 3, 0x0000 }, /* P0: Empty */
{ 1, 0, 0x0040 }, /* P1: Left USB 1 (OC0) */
{ 1, 1, 0x0040 }, /* P2: Left USB 2 (OC1) */
{ 1, 3, 0x0040 }, /* P3: SDCARD (no OC) */
{ 0, 3, 0x0000 }, /* P4: Empty */
{ 1, 3, 0x0040 }, /* P5: WWAN (no OC) */
{ 0, 3, 0x0000 }, /* P6: Empty */
{ 0, 3, 0x0000 }, /* P7: Empty */
/* Empty and onboard Ports 8-13, set to un-used pin OC4 */
{ 1, 4, 0x0040 }, /* P8: Camera (no OC) */
{ 1, 4, 0x0040 }, /* P9: Bluetooth (no OC) */
{ 0, 4, 0x0000 }, /* P10: Empty */
{ 0, 4, 0x0000 }, /* P11: Empty */
{ 0, 4, 0x0000 }, /* P12: Empty */
{ 0, 4, 0x0000 }, /* P13: Empty */
},
};
#if CONFIG_COLLECT_TIMESTAMPS
start_romstage_time = rdtsc();
#endif
if (bist == 0)
enable_lapic();
pch_enable_lpc();
/* Enable GPIOs */
pci_write_config32(PCH_LPC_DEV, GPIO_BASE, DEFAULT_GPIOBASE|1);
pci_write_config8(PCH_LPC_DEV, GPIO_CNTL, 0x10);
setup_pch_gpios(&link_gpio_map);
/* Initialize console device(s) */
console_init();
/* Halt if there was a built in self test failure */
report_bist_failure(bist);
if (MCHBAR16(SSKPD) == 0xCAFE) {
printk(BIOS_DEBUG, "soft reset detected\n");
boot_mode = 1;
/* System is not happy after keyboard reset... */
printk(BIOS_DEBUG, "Issuing CF9 warm reset\n");
outb(0x6, 0xcf9);
hlt();
}
/* Perform some early chipset initialization required
* before RAM initialization can work
*/
sandybridge_early_initialization(SANDYBRIDGE_MOBILE);
printk(BIOS_DEBUG, "Back from sandybridge_early_initialization()\n");
/* Check PM1_STS[15] to see if we are waking from Sx */
pm1_sts = inw(DEFAULT_PMBASE + PM1_STS);
/* Read PM1_CNT[12:10] to determine which Sx state */
pm1_cnt = inl(DEFAULT_PMBASE + PM1_CNT);
if ((pm1_sts & WAK_STS) && ((pm1_cnt >> 10) & 7) == 5) {
#if CONFIG_HAVE_ACPI_RESUME
printk(BIOS_DEBUG, "Resume from S3 detected.\n");
boot_mode = 2;
/* Clear SLP_TYPE. This will break stage2 but
* we care for that when we get there.
*/
outl(pm1_cnt & ~(7 << 10), DEFAULT_PMBASE + PM1_CNT);
#else
printk(BIOS_DEBUG, "Resume from S3 detected, but disabled.\n");
#endif
} else {
/* This is the fastest way to let users know
* the Intel CPU is now alive.
*/
google_chromeec_kbbacklight(100);
}
post_code(0x38);
/* Enable SPD ROMs and DDR-III DRAM */
enable_smbus();
/* Prepare USB controller early in S3 resume */
if (boot_mode == 2)
enable_usb_bar();
post_code(0x39);
copy_spd(&pei_data);
post_code(0x3a);
pei_data.boot_mode = boot_mode;
#if CONFIG_COLLECT_TIMESTAMPS
before_dram_time = rdtsc();
#endif
sdram_initialize(&pei_data);
#if CONFIG_COLLECT_TIMESTAMPS
after_dram_time = rdtsc();
#endif
post_code(0x3c);
rcba_config();
post_code(0x3d);
quick_ram_check();
post_code(0x3e);
MCHBAR16(SSKPD) = 0xCAFE;
#if CONFIG_EARLY_CBMEM_INIT
cbmem_was_initted = !cbmem_initialize();
#else
cbmem_was_initted = cbmem_reinit((uint64_t) (get_top_of_ram()
- HIGH_MEMORY_SIZE));
#endif
#if CONFIG_HAVE_ACPI_RESUME
/* If there is no high memory area, we didn't boot before, so
* this is not a resume. In that case we just create the cbmem toc.
*/
*(u32 *)CBMEM_BOOT_MODE = 0;
*(u32 *)CBMEM_RESUME_BACKUP = 0;
if ((boot_mode == 2) && cbmem_was_initted) {
void *resume_backup_memory = cbmem_find(CBMEM_ID_RESUME);
if (resume_backup_memory) {
*(u32 *)CBMEM_BOOT_MODE = boot_mode;
*(u32 *)CBMEM_RESUME_BACKUP = (u32)resume_backup_memory;
}
/* Magic for S3 resume */
pci_write_config32(PCI_DEV(0, 0x00, 0), SKPAD, 0xcafed00d);
} else if (boot_mode == 2) {
/* Failed S3 resume, reset to come up cleanly */
outb(0x6, 0xcf9);
hlt();
} else {
pci_write_config32(PCI_DEV(0, 0x00, 0), SKPAD, 0xcafebabe);
}
#endif
post_code(0x3f);
#if CONFIG_CHROMEOS
init_chromeos(boot_mode);
#endif
#if CONFIG_COLLECT_TIMESTAMPS
timestamp_init(base_time);
timestamp_add(TS_START_ROMSTAGE, start_romstage_time );
timestamp_add(TS_BEFORE_INITRAM, before_dram_time );
timestamp_add(TS_AFTER_INITRAM, after_dram_time );
timestamp_add_now(TS_END_ROMSTAGE);
#endif
#if CONFIG_CONSOLE_CBMEM
/* Keep this the last thing this function does. */
cbmemc_reinit();
#endif
}

32
src/mainboard/google/link/samsung_4Gb_1600_1.35v_x16.spd.hex Normal file
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92 11 0b 03 04 19 02 02
03 11 01 08 0a 00 fe 00
69 78 69 3c 69 11 18 81
f0 0a 3c 3c 01 40 83 01
00 80 00 00 00 00 00 00
00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00
00 00 00 00 0f 11 02 00
00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00
00 00 00 00 00 80 ce 01
00 00 00 00 00 00 6a 04
4d 34 37 31 42 35 36 37
34 42 48 30 2d 59 4b 30
20 20 00 00 80 ce 00 00
00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00

43
src/mainboard/google/link/thermal.h Normal file
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/*
* This file is part of the coreboot project.
*
* Copyright (C) 2011 Google Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
#ifndef LINK_THERMAL_H
#define LINK_THERMAL_H
/* Config TDP Sensor ID */
#define CTDP_SENSOR_ID 9 /* PECI */
/* Config TDP Nominal */
#define CTDP_NOMINAL_THRESHOLD_OFF 0
#define CTDP_NOMINAL_THRESHOLD_ON 0
/* Config TDP Down */
#define CTDP_DOWN_THRESHOLD_OFF 80
#define CTDP_DOWN_THRESHOLD_ON 90
/* Temperature which OS will shutdown at */
#define CRITICAL_TEMPERATURE 104
/* Temperature which OS will throttle CPU */
#define PASSIVE_TEMPERATURE 100
/* Tj_max value for calculating PECI CPU temperature */
#define MAX_TEMPERATURE 105
#endif