diff --git a/src/mainboard/intel/mtlrvp/variants/baseboard/mtlrvp_p/devicetree.cb b/src/mainboard/intel/mtlrvp/variants/baseboard/mtlrvp_p/devicetree.cb
index d28b7b1970..8cdbeea5a8 100644
--- a/src/mainboard/intel/mtlrvp/variants/baseboard/mtlrvp_p/devicetree.cb
+++ b/src/mainboard/intel/mtlrvp/variants/baseboard/mtlrvp_p/devicetree.cb
@@ -17,6 +17,25 @@ chip soc/intel/meteorlake
 		[PchSerialIoIndexUART2] = PchSerialIoDisabled,
 	}"
 
+	register "usb2_ports[0]" = "USB2_PORT_TYPE_C(OC0)" # USB2_C0
+	register "usb2_ports[1]" = "USB2_PORT_TYPE_C(OC0)" # USB2_C1
+	register "usb2_ports[2]" = "USB2_PORT_TYPE_C(OC0)" # USB2_C2
+	register "usb2_ports[3]" = "USB2_PORT_TYPE_C(OC0)" # USB2_C3
+	register "usb2_ports[4]" = "USB2_PORT_MID(OC0)" # Type-A Port A0
+	register "usb2_ports[5]" = "USB2_PORT_MID(OC0)" # Type-A Port A1
+	register "usb2_ports[6]" = "USB2_PORT_MID(OC_SKIP)" # FPS connector
+	register "usb2_ports[7]" = "USB2_PORT_MID(OC_SKIP)" # M.2 WWAN / MCF
+	register "usb2_ports[8]" = "USB2_PORT_MID(OC_SKIP)" # MCF / M.2 WWAN
+	register "usb2_ports[9]" = "USB2_PORT_MID(OC_SKIP)" # M.2 WLAN
+
+	register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC0)" # USB3.2_Type-A1 / M.2 WWAN
+	register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC0)" # USB3.2_Type-A0 / USB Flex Connector
+
+	register "tcss_ports[0]" = "TCSS_PORT_DEFAULT(OC0)"
+	register "tcss_ports[1]" = "TCSS_PORT_DEFAULT(OC0)"
+	register "tcss_ports[2]" = "TCSS_PORT_DEFAULT(OC0)"
+	register "tcss_ports[3]" = "TCSS_PORT_DEFAULT(OC0)"
+
 	device domain 0 on
 		device ref igpu on end
 		device ref heci1 on end