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- drop unneeded Makefile.inc 

- drop ap_romstage from Fam10 boards, the mechanism was never used on Fam10

Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5333 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
This commit is contained in:
Stefan Reinauer 2010-03-30 21:47:10 +00:00 committed by Stefan Reinauer
parent 0b2f18523a
commit 495b92b787
12 changed files with 1 additions and 725 deletions
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109
src/mainboard/amd/mahogany_fam10/ap_romstage.c
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@ -1,109 +0,0 @@
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2010 Advanced Micro Devices, Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
#define ASSEMBLY 1
#define __PRE_RAM__
#define RAMINIT_SYSINFO 1
#define CACHE_AS_RAM_ADDRESS_DEBUG 0
#define SET_NB_CFG_54 1
//used by raminit
#define QRANK_DIMM_SUPPORT 1
#include <stdint.h>
#include <device/pci_def.h>
#include <device/pci_ids.h>
#include <arch/io.h>
#include <device/pnp_def.h>
#include <arch/romcc_io.h>
#include <cpu/x86/lapic.h>
#include "option_table.h"
#include "pc80/mc146818rtc_early.c"
#include "pc80/serial.c"
#if CONFIG_USE_INIT == 0
#include "lib/memcpy.c"
#endif
#include "arch/i386/lib/console.c"
#include <cpu/amd/model_10xxx_rev.h>
#include "northbridge/amd/amdfam10/raminit.h"
#include "cpu/amd/model_fxx/apic_timer.c"
#include "lib/delay.c"
#if NODE_NUMS == 64
#define NODE_PCI(x,fn) ((x<32)?PCI_DEV(CONFIG_CBB,CONFIG_CDB+x,fn):PCI_DEV(CONFIG_CBB-1, CONFIG_CDB+x-32, fn))
#else
#define NODE_PCI(x, fn) PCI_DEV(CONFIG_CBB,CONFIG_CDB+x,fn)
#endif
//#include "cpu/x86/lapic/boot_cpu.c"
#include "northbridge/amd/amdfam10/reset_test.c"
#include "northbridge/amd/amdfam10/debug.c"
#include "southbridge/amd/amd8111/amd8111_early_ctrl.c"
#include "northbridge/amd/amdfam10/amdfam10.h"
#include "cpu/x86/mtrr.h"
#include "cpu/amd/mtrr.h"
#include "cpu/x86/tsc.h"
#include "northbridge/amd/amdfam10/amdfam10_pci.c"
#include "northbridge/amd/amdfam10/amdfam10_conf.c"
#include "northbridge/amd/amdfam10/raminit_ddr2_dqs.c"
#include "cpu/amd/quadcore/quadcore.c"
void hardwaremain(int ret_addr)
{
struct sys_info *sysinfo = (CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE); // in CACHE
struct sys_info *sysinfox = ((CONFIG_RAMTOP) - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE); // in RAM
struct node_core_id id;
id = get_node_core_id_x();
printk(BIOS_DEBUG, "CODE IN CACHE ON NODE: %02x\n");
train_ram(id.nodeid, sysinfo, sysinfox);
/* go back, but can not use stack any more, because we only keep
ret_addr and can not restore esp, and ebp */
__asm__ volatile (
"movl %0, %%edi\n\t"
"jmp *%%edi\n\t"
:: "a"(ret_addr)
);
}
#include <arch/registers.h>
void x86_exception(struct eregs *info)
{
do {
hlt();
} while(1);
}

109
src/mainboard/amd/serengeti_cheetah_fam10/ap_romstage.c
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@ -1,109 +0,0 @@
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2007 Advanced Micro Devices, Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
#define ASSEMBLY 1
#define __PRE_RAM__
#define RAMINIT_SYSINFO 1
#define CACHE_AS_RAM_ADDRESS_DEBUG 0
#define SET_NB_CFG_54 1
//used by raminit
#define QRANK_DIMM_SUPPORT 1
#include <stdint.h>
#include <device/pci_def.h>
#include <device/pci_ids.h>
#include <arch/io.h>
#include <device/pnp_def.h>
#include <arch/romcc_io.h>
#include <cpu/x86/lapic.h>
#include "option_table.h"
#include "pc80/mc146818rtc_early.c"
#include "pc80/serial.c"
#if CONFIG_USE_INIT == 0
#include "lib/memcpy.c"
#endif
#include "arch/i386/lib/console.c"
#include <cpu/amd/model_10xxx_rev.h>
#include "northbridge/amd/amdfam10/raminit.h"
#include "cpu/amd/model_fxx/apic_timer.c"
#include "lib/delay.c"
#if NODE_NUMS == 64
#define NODE_PCI(x,fn) ((x<32)?PCI_DEV(CONFIG_CBB,CONFIG_CDB+x,fn):PCI_DEV(CONFIG_CBB-1, CONFIG_CDB+x-32, fn))
#else
#define NODE_PCI(x, fn) PCI_DEV(CONFIG_CBB,CONFIG_CDB+x,fn)
#endif
//#include "cpu/x86/lapic/boot_cpu.c"
#include "northbridge/amd/amdfam10/reset_test.c"
#include "northbridge/amd/amdfam10/debug.c"
#include "southbridge/amd/amd8111/amd8111_early_ctrl.c"
#include "northbridge/amd/amdfam10/amdfam10.h"
#include "cpu/x86/mtrr.h"
#include "cpu/amd/mtrr.h"
#include "cpu/x86/tsc.h"
#include "northbridge/amd/amdfam10/amdfam10_pci.c"
#include "northbridge/amd/amdfam10/amdfam10_conf.c"
#include "northbridge/amd/amdfam10/raminit_ddr2_dqs.c"
#include "cpu/amd/quadcore/quadcore.c"
void hardwaremain(int ret_addr)
{
struct sys_info *sysinfo = (CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE); // in CACHE
struct sys_info *sysinfox = ((CONFIG_RAMTOP) - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE); // in RAM
struct node_core_id id;
id = get_node_core_id_x();
printk(BIOS_DEBUG, "CODE IN CACHE ON NODE: %02x\n");
train_ram(id.nodeid, sysinfo, sysinfox);
/* go back, but can not use stack any more, because we only keep
ret_addr and can not restore esp, and ebp */
__asm__ volatile (
"movl %0, %%edi\n\t"
"jmp *%%edi\n\t"
:: "a"(ret_addr)
);
}
#include <arch/registers.h>
void x86_exception(struct eregs *info)
{
do {
hlt();
} while(1);
}

22
src/mainboard/gigabyte/ga_2761gxdk/Makefile.inc
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@ -1,22 +0,0 @@
##
## This file is part of the coreboot project.
##
## Copyright (C) 2007-2008 coresystems GmbH
##
## This program is free software; you can redistribute it and/or modify
## it under the terms of the GNU General Public License as published by
## the Free Software Foundation; version 2 of the License.
##
## This program is distributed in the hope that it will be useful,
## but WITHOUT ANY WARRANTY; without even the implied warranty of
## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
## GNU General Public License for more details.
##
## You should have received a copy of the GNU General Public License
## along with this program; if not, write to the Free Software
## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
##
#needed by irq_tables and mptable and acpi_tables
obj-$(CONFIG_USE_INIT) += romstage.o
obj-$(CONFIG_AP_CODE_IN_CAR) += ap_romstage.o

3
src/mainboard/gigabyte/m57sli/Makefile.inc
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@ -17,7 +17,4 @@
## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
## ##
#needed by irq_tables and mptable and acpi_tables
obj-$(CONFIG_USE_INIT) += romstage.o
obj-$(CONFIG_AP_CODE_IN_CAR) += ap_romstage.o
obj-$(CONFIG_SUPERIO_ITE_IT8716F_OVERRIDE_FANCTL) += fanctl.o obj-$(CONFIG_SUPERIO_ITE_IT8716F_OVERRIDE_FANCTL) += fanctl.o

22
src/mainboard/msi/ms7260/Makefile.inc
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@ -1,22 +0,0 @@
##
## This file is part of the coreboot project.
##
## Copyright (C) 2007-2008 coresystems GmbH
##
## This program is free software; you can redistribute it and/or modify
## it under the terms of the GNU General Public License as published by
## the Free Software Foundation; version 2 of the License.
##
## This program is distributed in the hope that it will be useful,
## but WITHOUT ANY WARRANTY; without even the implied warranty of
## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
## GNU General Public License for more details.
##
## You should have received a copy of the GNU General Public License
## along with this program; if not, write to the Free Software
## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
##
#needed by irq_tables and mptable and acpi_tables
obj-$(CONFIG_USE_INIT) += romstage.o
obj-$(CONFIG_AP_CODE_IN_CAR) += ap_romstage.o

4
src/mainboard/msi/ms9282/Makefile.inc
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@ -17,9 +17,7 @@
## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
## ##
# FIXME drivers should be selected through Kconfig
obj-y += ../../../drivers/i2c/i2cmux2/i2cmux2.o obj-y += ../../../drivers/i2c/i2cmux2/i2cmux2.o
obj-y += ../../../drivers/i2c/adm1027/adm1027.o obj-y += ../../../drivers/i2c/adm1027/adm1027.o
#needed by irq_tables and mptable and acpi_tables
obj-$(CONFIG_USE_INIT) += romstage.o
obj-$(CONFIG_AP_CODE_IN_CAR) += ap_romstage.o

22
src/mainboard/nvidia/l1_2pvv/Makefile.inc
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@ -1,22 +0,0 @@
##
## This file is part of the coreboot project.
##
## Copyright (C) 2007-2008 coresystems GmbH
##
## This program is free software; you can redistribute it and/or modify
## it under the terms of the GNU General Public License as published by
## the Free Software Foundation; version 2 of the License.
##
## This program is distributed in the hope that it will be useful,
## but WITHOUT ANY WARRANTY; without even the implied warranty of
## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
## GNU General Public License for more details.
##
## You should have received a copy of the GNU General Public License
## along with this program; if not, write to the Free Software
## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
##
#needed by irq_tables and mptable and acpi_tables
obj-$(CONFIG_USE_INIT) += romstage.o
obj-$(CONFIG_AP_CODE_IN_CAR) += ap_romstage.o

137
src/mainboard/supermicro/h8dmr_fam10/ap_romstage.c
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@ -1,137 +0,0 @@
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2007 AMD
* Written by Yinghai Lu <yinghailu@amd.com> for AMD.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
#define ASSEMBLY 1
#define __PRE_RAM__
#define RAMINIT_SYSINFO 1
#define CACHE_AS_RAM_ADDRESS_DEBUG 0
#define SET_NB_CFG_54 1
//used by raminit
#define QRANK_DIMM_SUPPORT 1
#define K8_REV_F_SUPPORT_F0_F1_WORKAROUND 0
#include <stdint.h>
#include <device/pci_def.h>
#include <device/pci_ids.h>
#include <arch/io.h>
#include <device/pnp_def.h>
#include <arch/romcc_io.h>
#include <cpu/x86/lapic.h>
#include "option_table.h"
#include "pc80/mc146818rtc_early.c"
#include "pc80/serial.c"
#if CONFIG_USE_INIT == 0
#include "lib/memcpy.c"
#endif
#include "arch/i386/lib/console.c"
#include "lib/uart8250.c"
#include "console/vtxprintf.c"
#include "./arch/i386/lib/printk_init.c"
#if 0
static void post_code(uint8_t value) {
#if 1
int i;
for(i=0;i<0x80000;i++) {
outb(value, 0x80);
}
#endif
}
#endif
#include <cpu/amd/model_fxx_rev.h>
#include "northbridge/amd/amdk8/raminit.h"
#include "cpu/amd/model_fxx/apic_timer.c"
#include "lib/delay.c"
//#include "cpu/x86/lapic/boot_cpu.c"
#include "northbridge/amd/amdk8/reset_test.c"
#include "northbridge/amd/amdk8/debug.c"
#include "southbridge/nvidia/mcp55/mcp55_early_ctrl.c"
#include "northbridge/amd/amdk8/amdk8_f.h"
#include "cpu/x86/mtrr.h"
#include "cpu/amd/mtrr.h"
#include "cpu/x86/tsc.h"
#include "northbridge/amd/amdk8/amdk8_f_pci.c"
#include "northbridge/amd/amdk8/raminit_f_dqs.c"
static inline unsigned get_nodes(void)
{
return ((pci_read_config32(PCI_DEV(0, 0x18, 0), 0x60)>>4) & 7) + 1;
}
#include "cpu/amd/dualcore/dualcore.c"
void hardwaremain(int ret_addr)
{
struct sys_info *sysinfo = (DCACHE_RAM_BASE + DCACHE_RAM_SIZE - DCACHE_RAM_GLOBAL_VAR_SIZE); // in CACHE
struct sys_info *sysinfox = ((CONFIG_RAMTOP) - DCACHE_RAM_GLOBAL_VAR_SIZE); // in RAM
struct node_core_id id;
id = get_node_core_id_x();
print_debug("CODE IN CACHE ON NODE:"); print_debug_hex8(id.nodeid); print_debug("\r\n");
train_ram(id.nodeid, sysinfo, sysinfox);
/*
go back, but can not use stack any more, because we only keep ret_addr and can not restore esp, and ebp
*/
__asm__ volatile (
"movl %0, %%edi\n\t"
"jmp *%%edi\n\t"
:: "a"(ret_addr)
);
}
struct eregs {
uint32_t eax, ecx, edx, ebx, esp, ebp, esi, edi;
uint32_t vector;
uint32_t error_code;
uint32_t eip;
uint32_t cs;
uint32_t eflags;
};
void x86_exception(struct eregs *info)
{
do {
hlt();
} while(1);
}

141
src/mainboard/supermicro/h8qme_fam10/ap_romstage.c
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@ -1,141 +0,0 @@
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2007 AMD
* Written by Yinghai Lu <yinghailu@amd.com> for AMD.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
#define ASSEMBLY 1
#define __PRE_RAM__
#define RAMINIT_SYSINFO 1
#define CACHE_AS_RAM_ADDRESS_DEBUG 0
#define SET_NB_CFG_54 1
//used by raminit
#define QRANK_DIMM_SUPPORT 1
#define K8_REV_F_SUPPORT_F0_F1_WORKAROUND 0
#include <stdint.h>
#include <device/pci_def.h>
#include <device/pci_ids.h>
#include <arch/io.h>
#include <device/pnp_def.h>
#include <arch/romcc_io.h>
#include <cpu/x86/lapic.h>
#include "option_table.h"
#include "pc80/mc146818rtc_early.c"
#include "pc80/serial.c"
#if CONFIG_USE_INIT == 0
#include "lib/memcpy.c"
#endif
#include "arch/i386/lib/console.c"
#include "lib/uart8250.c"
#include "console/vtxprintf.c"
#include "./arch/i386/lib/printk_init.c"
#if 0
static void post_code(uint8_t value) {
#if 1
int i;
for(i=0;i<0x80000;i++) {
outb(value, 0x80);
}
#endif
}
#endif
#include <cpu/amd/model_fxx_rev.h>
#include "northbridge/amd/amkfam10/raminit.h"
#include "cpu/amd/model_fxx/apic_timer.c"
#include "lib/delay.c"
//#include "cpu/x86/lapic/boot_cpu.c"
#include "northbridge/amd/amdfam10/reset_test.c"
#include "northbridge/amd/amdfam10/debug.c"
#include "southbridge/nvidia/mcp55/mcp55_early_ctrl.c"
#include "northbridge/amd/amdfam10/amdfam10.h"
#include "cpu/x86/mtrr.h"
#include "cpu/amd/mtrr.h"
#include "cpu/x86/tsc.h"
#include "northbridge/amd/amdfam10/amdfam10_pci.c"
#include "northbridge/amd/amdk8/raminit_f_dqs.c"
//#include "northbridge/amd/amdfam10/raminit_f_dqs.c"
static inline unsigned get_nodes(void)
{
return ((pci_read_config32(PCI_DEV(0, 0x18, 0), 0x60)>>4) & 7) + 1;
}
//#include "cpu/amd/dualcore/dualcore.c"
#include "cpu/amd/quadcore/quadcore.c"
void hardwaremain(int ret_addr)
{
struct sys_info *sysinfo = (DCACHE_RAM_BASE + DCACHE_RAM_SIZE - DCACHE_RAM_GLOBAL_VAR_SIZE); // in CACHE
struct sys_info *sysinfox = ((CONFIG_RAMTOP) - DCACHE_RAM_GLOBAL_VAR_SIZE); // in RAM
struct node_core_id id;
id = get_node_core_id_x();
print_debug("CODE IN CACHE ON NODE:"); print_debug_hex8(id.nodeid); print_debug("\r\n");
train_ram(id.nodeid, sysinfo, sysinfox);
/*
go back, but can not use stack any more, because we only keep ret_addr and can not restore esp, and ebp
*/
__asm__ volatile (
"movl %0, %%edi\n\t"
"jmp *%%edi\n\t"
:: "a"(ret_addr)
);
}
struct eregs {
uint32_t eax, ecx, edx, ebx, esp, ebp, esi, edi;
uint32_t vector;
uint32_t error_code;
uint32_t eip;
uint32_t cs;
uint32_t eflags;
};
void x86_exception(struct eregs *info)
{
do {
hlt();
} while(1);
}

22
src/mainboard/tyan/s2912/Makefile.inc
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@ -1,22 +0,0 @@
##
## This file is part of the coreboot project.
##
## Copyright (C) 2007-2008 coresystems GmbH
##
## This program is free software; you can redistribute it and/or modify
## it under the terms of the GNU General Public License as published by
## the Free Software Foundation; version 2 of the License.
##
## This program is distributed in the hope that it will be useful,
## but WITHOUT ANY WARRANTY; without even the implied warranty of
## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
## GNU General Public License for more details.
##
## You should have received a copy of the GNU General Public License
## along with this program; if not, write to the Free Software
## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
##
#needed by irq_tables and mptable and acpi_tables
obj-$(CONFIG_USE_INIT) += romstage.o
obj-$(CONFIG_AP_CODE_IN_CAR) += ap_romstage.o

22
src/mainboard/tyan/s2912_fam10/Makefile.inc
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@ -1,22 +0,0 @@
##
## This file is part of the coreboot project.
##
## Copyright (C) 2007-2008 coresystems GmbH
##
## This program is free software; you can redistribute it and/or modify
## it under the terms of the GNU General Public License as published by
## the Free Software Foundation; version 2 of the License.
##
## This program is distributed in the hope that it will be useful,
## but WITHOUT ANY WARRANTY; without even the implied warranty of
## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
## GNU General Public License for more details.
##
## You should have received a copy of the GNU General Public License
## along with this program; if not, write to the Free Software
## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
##
#needed by irq_tables and mptable and acpi_tables
obj-$(CONFIG_USE_INIT) += romstage.o
obj-$(CONFIG_AP_CODE_IN_CAR) += ap_romstage.o

113
src/mainboard/tyan/s2912_fam10/ap_romstage.c
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@ -1,113 +0,0 @@
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2007 AMD
* Written by Yinghai Lu <yinghailu@amd.com> for AMD.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
#define ASSEMBLY 1
#define __PRE_RAM__
#define RAMINIT_SYSINFO 1
#define CACHE_AS_RAM_ADDRESS_DEBUG 0
#define SET_NB_CFG_54 1
//used by raminit
#define QRANK_DIMM_SUPPORT 1
#define K8_REV_F_SUPPORT_F0_F1_WORKAROUND 0
#include <stdint.h>
#include <device/pci_def.h>
#include <device/pci_ids.h>
#include <arch/io.h>
#include <device/pnp_def.h>
#include <arch/romcc_io.h>
#include <cpu/x86/lapic.h>
#include "option_table.h"
#include "pc80/mc146818rtc_early.c"
#include "pc80/serial.c"
#if CONFIG_USE_INIT == 0
#include "lib/memcpy.c"
#endif
#include "arch/i386/lib/console.c"
#include <cpu/amd/model_fxx_rev.h>
#include "northbridge/amd/amdk8/raminit.h"
#include "cpu/amd/model_fxx/apic_timer.c"
#include "lib/delay.c"
//#include "cpu/x86/lapic/boot_cpu.c"
#include "northbridge/amd/amdk8/reset_test.c"
#include "northbridge/amd/amdk8/debug.c"
#include "southbridge/nvidia/mcp55/mcp55_early_ctrl.c"
#include "northbridge/amd/amdk8/amdk8_f.h"
#include "cpu/x86/mtrr.h"
#include "cpu/amd/mtrr.h"
#include "cpu/x86/tsc.h"
#include "northbridge/amd/amdk8/amdk8_f_pci.c"
#include "northbridge/amd/amdk8/raminit_f_dqs.c"
#include "cpu/amd/dualcore/dualcore.c"
void hardwaremain(int ret_addr)
{
struct sys_info *sysinfo = (CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE); // in CACHE
struct sys_info *sysinfox = ((CONFIG_RAMTOP) - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE); // in RAM
struct node_core_id id;
id = get_node_core_id_x();
//FIXME: for USBDEBUG_DIRECT you need to make sure dbg_info get assigned in AP
print_debug("CODE IN CACHE ON NODE:"); print_debug_hex8(id.nodeid); print_debug("\r\n");
train_ram(id.nodeid, sysinfo, sysinfox);
/*
go back, but can not use stack any more, because we only keep ret_addr and can not restore esp, and ebp
*/
__asm__ volatile (
"movl %0, %%edi\n\t"
"jmp *%%edi\n\t"
:: "a"(ret_addr)
);
}
#include <arch/registers.h>
void x86_exception(struct eregs *info)
{
do {
hlt();
} while(1);
}