src: Capitalize Super I/O
Change-Id: I9ad9294dd2ae3e4a8a9069ac6464ad753af65ea5 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35541 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
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@ -70,7 +70,7 @@ facing towards the bottom of the board.
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- The VGA port doesn't work until the OS reinitialises the display.
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- The VGA port doesn't work until the OS reinitialises the display.
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- There is no automatic, OS-independent fan control. This is because
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- There is no automatic, OS-independent fan control. This is because
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the super I/O hardware monitor can only obtain valid CPU temperature
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the Super I/O hardware monitor can only obtain valid CPU temperature
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readings from the PECI agent, but the required driver doesn't exist
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readings from the PECI agent, but the required driver doesn't exist
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in coreboot. The `coretemp` driver can still be used for accurate CPU
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in coreboot. The `coretemp` driver can still be used for accurate CPU
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temperature readings from an OS.
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temperature readings from an OS.
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@ -49,7 +49,7 @@ region is not readable even by the host.
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suspend.
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suspend.
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- There is no automatic, OS-independent fan control. This is because
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- There is no automatic, OS-independent fan control. This is because
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the super I/O hardware monitor can only obtain valid CPU temperature
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the Super I/O hardware monitor can only obtain valid CPU temperature
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readings from the PECI agent, whose complete initialisation is not
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readings from the PECI agent, whose complete initialisation is not
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publicly documented. The `coretemp` driver can still be used for
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publicly documented. The `coretemp` driver can still be used for
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accurate CPU temperature readings.
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accurate CPU temperature readings.
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@ -46,7 +46,7 @@ region is not readable even by the host.
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## Known issues
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## Known issues
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- There is no automatic, OS-independent fan control. This is because
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- There is no automatic, OS-independent fan control. This is because
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the super I/O hardware monitor can only obtain valid CPU temperature
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the Super I/O hardware monitor can only obtain valid CPU temperature
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readings from the PECI agent, whose complete initialisation is not
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readings from the PECI agent, whose complete initialisation is not
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publicly documented. The `coretemp` driver can still be used for
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publicly documented. The `coretemp` driver can still be used for
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accurate CPU temperature readings.
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accurate CPU temperature readings.
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@ -168,7 +168,7 @@ Please also see :doc:`../../northbridge/intel/haswell/known-issues`.
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- VGA graphics
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- VGA graphics
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- disabling VGA graphics using the jumper
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- disabling VGA graphics using the jumper
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- hiding the AST2400 using the CMOS setting
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- hiding the AST2400 using the CMOS setting
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- super I/O hardware monitor (see [Known issues](#known-issues))
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- Super I/O hardware monitor (see [Known issues](#known-issues))
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- initialisation with Haswell MRC version 1.6.1 build 2
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- initialisation with Haswell MRC version 1.6.1 build 2
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- flashrom under coreboot
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- flashrom under coreboot
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- Wake-on-LAN
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- Wake-on-LAN
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@ -109,7 +109,7 @@ void pnp_read_resources(struct device *dev)
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static void pnp_set_resource(struct device *dev, struct resource *resource)
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static void pnp_set_resource(struct device *dev, struct resource *resource)
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{
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{
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if (!(resource->flags & IORESOURCE_ASSIGNED)) {
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if (!(resource->flags & IORESOURCE_ASSIGNED)) {
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/* The PNP_MSC super IO registers have the IRQ flag set. If no
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/* The PNP_MSC Super IO registers have the IRQ flag set. If no
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value is assigned in the devicetree, the corresponding
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value is assigned in the devicetree, the corresponding
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PNP_MSC register doesn't get written, which should be printed
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PNP_MSC register doesn't get written, which should be printed
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as warning and not as error. */
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as warning and not as error. */
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@ -1 +1 @@
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/* no super i/o */
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/* no Super I/O */
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@ -20,9 +20,9 @@
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*
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*
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* Controlled by the following preprocessor defines:
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* Controlled by the following preprocessor defines:
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*
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*
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* SUPERIO_CHIP_NAME The name of the super i/o chip (unique, required)
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* SUPERIO_CHIP_NAME The name of the Super I/O chip (unique, required)
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* SUPERIO_PNP_HID The EisaId string that identifies this device (optional)
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* SUPERIO_PNP_HID The EisaId string that identifies this device (optional)
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* SUPERIO_PNP_LDN The logical device number on the super i/o
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* SUPERIO_PNP_LDN The logical device number on the Super I/O
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* chip for this device (required)
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* chip for this device (required)
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* SUPERIO_PNP_DDN A string literal that identifies the dos device
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* SUPERIO_PNP_DDN A string literal that identifies the dos device
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* name (DDN) of this device (e.g. "COM1", optional)
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* name (DDN) of this device (e.g. "COM1", optional)
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@ -22,8 +22,8 @@
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*
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*
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* Controlled by the following preprocessor defines:
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* Controlled by the following preprocessor defines:
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*
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*
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* SUPERIO_CHIP_NAME The name of the super i/o chip (unique, required)
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* SUPERIO_CHIP_NAME The name of the Super I/O chip (unique, required)
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* SUPERIO_KBC_LDN The logical device number on the super i/o
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* SUPERIO_KBC_LDN The logical device number on the Super I/O
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* chip for this keyboard controller (required)
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* chip for this keyboard controller (required)
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* SUPERIO_KBC_PS2M If defined, PS/2 mouse support is included in
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* SUPERIO_KBC_PS2M If defined, PS/2 mouse support is included in
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* the KBC_LDN. Mouse irq is set at IRQ1 of the
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* the KBC_LDN. Mouse irq is set at IRQ1 of the
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@ -21,8 +21,8 @@
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*
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*
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* Controlled by the following preprocessor defines:
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* Controlled by the following preprocessor defines:
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*
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*
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* SUPERIO_CHIP_NAME The name of the super i/o chip (unique, required)
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* SUPERIO_CHIP_NAME The name of the Super I/O chip (unique, required)
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* SUPERIO_UART_LDN The logical device number on the super i/o
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* SUPERIO_UART_LDN The logical device number on the Super I/O
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* chip for this UART (required)
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* chip for this UART (required)
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* SUPERIO_UART_DDN A string literal that identifies the dos device
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* SUPERIO_UART_DDN A string literal that identifies the dos device
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* name (DDN) of this uart (e.g. "COM1", optional)
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* name (DDN) of this uart (e.g. "COM1", optional)
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