Following patch adds support for resume on VT8237 based motherboards. The NB
part of this patch adds support for resume well NVRAM. In which DQS values are stored. Signed-off-by: Rudolf Marek <r.marek@assembler.cz> Acked-by: Peter Stuge <peter@stuge.se> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4100 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
This commit is contained in:
Rudolf Marek
parent
a572f83e71
commit
497c8effce
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@ -29,6 +29,9 @@
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*/
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#define K8T890_APIC_BASE 0xfecc0000
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/* The 256 bytes of NVRAM for S3 storage, 256B aligned */
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#define K8T890_NVRAM_IO_BASE 0xf00
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#define K8T890_MMCONFIG_MBAR 0x61
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#define K8T890_MULTIPLE_FN_EN 0x4f
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@ -36,6 +39,7 @@
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#define K8M890_FBSIZEMB 64
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#include <device/device.h>
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extern void writeback(struct device *dev, u16 where, u8 what);
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extern void dump_south(device_t dev);
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@ -23,6 +23,15 @@
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*/
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#include <stdlib.h>
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//include "k8t890.h"
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#warning hack the right header here
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/* The 256 bytes of NVRAM for S3 storage, 256B aligned */
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#define K8T890_NVRAM_IO_BASE 0xf00
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#define K8T890_MULTIPLE_FN_EN 0x4f
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/* we provide S3 NVRAM to system */
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#define S3_NVRAM_EARLY 1
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/* AMD K8 LDT0, LDT1, LDT2 Link Control Registers */
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static ldtreg[3] = {0x86, 0xa6, 0xc6};
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@ -33,10 +42,22 @@ static ldtreg[3] = {0x86, 0xa6, 0xc6};
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u8 k8t890_early_setup_ht(void)
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{
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u8 awidth, afreq, cldtfreq;
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u8 awidth, afreq, cldtfreq, reg;
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u8 cldtwidth_in, cldtwidth_out, vldtwidth_in, vldtwidth_out, ldtnr, width;
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u16 vldtcaps;
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/* hack, enable NVRAM in chipset */
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pci_write_config8(PCI_DEV(0, 0x0, 0), K8T890_MULTIPLE_FN_EN, 0x01);
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/*
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* NVRAM I/O base at K8T890_NVRAM_IO_BASE
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*/
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pci_write_config8(PCI_DEV(0, 0x0, 2), 0xa2, (K8T890_NVRAM_IO_BASE >> 8));
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reg = pci_read_config8(PCI_DEV(0, 0x0, 2), 0xa1);
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reg |= 0x1;
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pci_write_config8(PCI_DEV(0, 0x0, 2), 0xa1, reg);
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/* check if connected non coherent, initcomplete (find the SB on K8 side) */
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if (0x7 == pci_read_config8(PCI_DEV(0, 0x18, 0), 0x98)) {
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ldtnr = 0;
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@ -90,3 +111,44 @@ u8 k8t890_early_setup_ht(void)
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return 1;
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}
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int s3_save_nvram_early(u32 dword, int size, int nvram_pos) {
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printk_debug("Writing %x of size %d to nvram pos: %d\n", dword, size, nvram_pos);
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switch (size) {
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case 1:
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outb((dword & 0xff), K8T890_NVRAM_IO_BASE+nvram_pos);
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nvram_pos +=1;
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break;
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case 2:
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outw((dword & 0xffff), K8T890_NVRAM_IO_BASE+nvram_pos);
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nvram_pos +=2;
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break;
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default:
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outl(dword, K8T890_NVRAM_IO_BASE+nvram_pos);
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nvram_pos +=4;
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break;
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}
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return nvram_pos;
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}
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int s3_load_nvram_early(int size, u32 *old_dword, int nvram_pos) {
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switch (size) {
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case 1:
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*old_dword &= ~0xff;
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*old_dword |= inb(K8T890_NVRAM_IO_BASE+nvram_pos);
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nvram_pos +=1;
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break;
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case 2:
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*old_dword &= ~0xffff;
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*old_dword |= inw(K8T890_NVRAM_IO_BASE+nvram_pos);
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nvram_pos +=2;
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break;
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default:
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*old_dword = inl(K8T890_NVRAM_IO_BASE+nvram_pos);
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nvram_pos +=4;
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break;
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}
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printk_debug("Loading %x of size %d to nvram pos:%d\n", * old_dword, size, nvram_pos-size);
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return nvram_pos;
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}
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@ -37,14 +37,14 @@ static void host_ctrl_enable_k8t890(struct device *dev)
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*/
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pci_write_config8(dev, 0xa0, 0x13);
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/* Disable NVRAM and enable non-posted PCI writes. */
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pci_write_config8(dev, 0xa1, 0x8e);
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/*
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* NVRAM I/O base 0xe00-0xeff, but it is disabled.
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* NVRAM I/O base at K8T890_NVRAM_IO_BASE
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* Some bits are set and reserved.
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*/
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pci_write_config8(dev, 0xa2, 0x0e);
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pci_write_config8(dev, 0xa2, (K8T890_NVRAM_IO_BASE >> 8));
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/* enable NB NVRAM and enable non-posted PCI writes. */
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pci_write_config8(dev, 0xa1, 0x8f);
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/* Arbitration control, some bits are reserved. */
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pci_write_config8(dev, 0xa5, 0x3c);
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@ -95,14 +95,15 @@ static void host_ctrl_enable_k8m890(struct device *dev) {
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*/
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pci_write_config8(dev, 0xa0, 0x13);
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/* Disable NVRAM and enable non-posted PCI writes. */
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pci_write_config8(dev, 0xa1, 0x8e);
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/*
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* NVRAM I/O base 0xe00-0xeff, but it is disabled.
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* NVRAM I/O base at K8T890_NVRAM_IO_BASE
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*/
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pci_write_config8(dev, 0xa2, 0x0e);
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pci_write_config8(dev, 0xa2, (K8T890_NVRAM_IO_BASE >> 8));
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/* Enable NVRAM and enable non-posted PCI writes. */
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pci_write_config8(dev, 0xa1, 0x8f);
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/* Arbitration control */
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pci_write_config8(dev, 0xa5, 0x3c);
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@ -294,6 +294,37 @@ void enable_rom_decode(void)
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pci_write_config8(dev, 0x41, 0x7f);
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}
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#define ACPI_IS_WAKEUP_EARLY 1
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int acpi_is_wakeup_early(void) {
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device_t dev;
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u16 tmp;
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print_debug("IN TEST WAKEUP\n");
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/* Power management controller */
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dev = pci_locate_device(PCI_ID(PCI_VENDOR_ID_VIA,
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PCI_DEVICE_ID_VIA_VT8237R_LPC), 0);
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if (dev == PCI_DEV_INVALID) {
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/* Power management controller */
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dev = pci_locate_device(PCI_ID(PCI_VENDOR_ID_VIA,
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PCI_DEVICE_ID_VIA_VT8237S_LPC), 0);
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if (dev == PCI_DEV_INVALID)
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die("Power management controller not found\r\n");
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}
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/* Set ACPI base address to I/O VT8237R_ACPI_IO_BASE. */
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pci_write_config16(dev, 0x88, VT8237R_ACPI_IO_BASE | 0x1);
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/* Enable ACPI accessm RTC signal gated with PSON. */
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pci_write_config8(dev, 0x81, 0x84);
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tmp = inw(VT8237R_ACPI_IO_BASE + 0x04);
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print_debug_hex8(tmp);
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return ((tmp & (7 << 10)) >> 10) == 1 ? 3 : 0 ;
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}
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#if defined(__GNUC__)
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void vt8237_early_spi_init(void)
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{
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@ -149,8 +149,13 @@ static void pci_routing_fixup(struct device *dev)
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* Set up the power management capabilities directly into ACPI mode.
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* This avoids having to handle any System Management Interrupts (SMIs).
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*/
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extern u8 acpi_slp_type;
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static void setup_pm(device_t dev)
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{
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u16 tmp;
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/* Debounce LID and PWRBTN# Inputs for 16ms. */
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pci_write_config8(dev, 0x80, 0x20);
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@ -171,10 +176,10 @@ static void setup_pm(device_t dev)
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/*
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* 7 = SMBus clock from RTC 32.768KHz
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* 5 = Internal PLL reset from susp
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* 2 = GPO2 is GPIO
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* 5 = Internal PLL reset from susp disabled
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* 2 = GPO2 is SUSA#
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*/
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pci_write_config8(dev, 0x94, 0xa4);
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pci_write_config8(dev, 0x94, 0xa0);
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/*
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* 7 = stp to sust delay 1msec
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@ -219,7 +224,17 @@ static void setup_pm(device_t dev)
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outb(0x0, VT8237R_ACPI_IO_BASE + 0x42);
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/* SCI is generated for RTC/pwrBtn/slpBtn. */
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outw(0x001, VT8237R_ACPI_IO_BASE + 0x04);
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tmp = inw(VT8237R_ACPI_IO_BASE + 0x04);
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acpi_slp_type = ((tmp & (7 << 10)) >> 10) == 1 ? 3 : 0 ;
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printk_debug("SLP_TYP type was %x %x\n", tmp, acpi_slp_type);
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/* clear sleep */
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tmp &= ~(7 << 10);
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tmp |= 1;
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outw(tmp, VT8237R_ACPI_IO_BASE + 0x04);
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}
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static void vt8237r_init(struct device *dev)
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