diff --git a/src/mainboard/google/rush/memlayout.ld b/src/mainboard/google/rush/memlayout.ld
index 5bd72e5126..d8fdb9a94b 100644
--- a/src/mainboard/google/rush/memlayout.ld
+++ b/src/mainboard/google/rush/memlayout.ld
@@ -1,5 +1,5 @@
 #if IS_ENABLED(CONFIG_VBOOT2_VERIFY_FIRMWARE)
 #include <soc/memlayout_vboot2.ld>
 #else
-#include <soc/memlayout_vboot.ld>
+#include <soc/memlayout.ld>
 #endif
diff --git a/src/mainboard/google/rush_ryu/memlayout.ld b/src/mainboard/google/rush_ryu/memlayout.ld
index 5bd72e5126..d8fdb9a94b 100644
--- a/src/mainboard/google/rush_ryu/memlayout.ld
+++ b/src/mainboard/google/rush_ryu/memlayout.ld
@@ -1,5 +1,5 @@
 #if IS_ENABLED(CONFIG_VBOOT2_VERIFY_FIRMWARE)
 #include <soc/memlayout_vboot2.ld>
 #else
-#include <soc/memlayout_vboot.ld>
+#include <soc/memlayout.ld>
 #endif
diff --git a/src/soc/nvidia/tegra132/include/soc/memlayout_vboot.ld b/src/soc/nvidia/tegra132/include/soc/memlayout.ld
similarity index 89%
rename from src/soc/nvidia/tegra132/include/soc/memlayout_vboot.ld
rename to src/soc/nvidia/tegra132/include/soc/memlayout.ld
index c097c3cd6a..a7e3635c87 100644
--- a/src/soc/nvidia/tegra132/include/soc/memlayout_vboot.ld
+++ b/src/soc/nvidia/tegra132/include/soc/memlayout.ld
@@ -32,12 +32,13 @@ SECTIONS
 {
 	SRAM_START(0x40000000)
 	PRERAM_CBMEM_CONSOLE(0x40000000, 8K)
-	CBFS_CACHE(0x40002000, 88K)
-	STACK(0x40018000, 16K)
-	BOOTBLOCK(0x4001C000, 20K)
+	PRERAM_CBFS_CACHE(0x40002000, 84K)
+	STACK(0x40017000, 16K)
+	BOOTBLOCK(0x4001B800, 22K)
 	ROMSTAGE(0x40021000, 124K)
 	SRAM_END(0x40040000)
 
 	DRAM_START(0x80000000)
-	RAMSTAGE(0x80200000, 192K)
+	POSTRAM_CBFS_CACHE(0x80100000, 1M)
+	RAMSTAGE(0x80200000, 256K)
 }