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i82801gx: enable SPI prefetching 

Signed-off-by: Sven Schnelle <svens@stackframe.org>
Acked-by: Sven Schnelle <svens@stackframe.org>

git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6553 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
This commit is contained in:
Sven Schnelle 2011-05-03 07:55:30 +00:00
parent 8eee19d0ea
commit 49ae971333
2 changed files with 45 additions and 0 deletions
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5
src/southbridge/intel/i82801gx/Kconfig
View File

@ -38,5 +38,10 @@ config USBDEBUG_DEFAULT_PORT
int int
default 1 default 1
config BOOTBLOCK_SOUTHBRIDGE_INIT
string
default "southbridge/intel/i82801gx/bootblock.c"
depends on SOUTHBRIDGE_INTEL_I82801GX
endif endif

40
src/southbridge/intel/i82801gx/bootblock.c Normal file
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@ -0,0 +1,40 @@
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2011 Sven Schnelle <svens@stackframe.org>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
#include <arch/io.h>
#include <arch/romcc_io.h>
static void enable_spi_prefetch(void)
{
u8 reg8;
device_t dev;
dev = PCI_DEV(0, 0x1f, 0);
reg8 = pci_read_config8(dev, 0xdc);
reg8 &= ~(3 << 2);
reg8 |= (2 << 2); /* Prefetching and Caching Enabled */
pci_write_config8(dev, 0xdc, reg8);
}
static void bootblock_southbridge_init(void)
{
enable_spi_prefetch();
}