diff --git a/Makefile.inc b/Makefile.inc
index fca7ebdedd..7149c4f63f 100644
--- a/Makefile.inc
+++ b/Makefile.inc
@@ -1177,10 +1177,8 @@ $(CONFIG_CBFS_PREFIX)/romstage-options := -S ".car.data"
 ifneq ($(CONFIG_NO_XIP_EARLY_STAGES),y)
 $(CONFIG_CBFS_PREFIX)/romstage-options += --xip
 
-# If XIP_ROM_SIZE isn't being used don't overly constrain romstage by passing
-# -P with a default value.
 ifneq ($(CONFIG_NO_FIXED_XIP_ROM_SIZE),y)
-$(CONFIG_CBFS_PREFIX)/romstage-options += -P $(CONFIG_XIP_ROM_SIZE)
+$(CONFIG_CBFS_PREFIX)/romstage-options += --pow2page
 endif    # CONFIG_NO_FIXED_XIP_ROM_SIZE
 
 endif   # CONFIG_NO_XIP_EARLY_STAGES
diff --git a/src/cpu/x86/Kconfig b/src/cpu/x86/Kconfig
index 4260278e02..07dfe45e64 100644
--- a/src/cpu/x86/Kconfig
+++ b/src/cpu/x86/Kconfig
@@ -70,11 +70,6 @@ config NO_FIXED_XIP_ROM_SIZE
 	  to unnecessary alignment constraints in cbfs for romstage.
 	  Therefore, allow those chipsets a path to not be burdened.
 
-config XIP_ROM_SIZE
-	hex
-	depends on !NO_FIXED_XIP_ROM_SIZE
-	default 0x10000
-
 config SETUP_XIP_CACHE
 	bool
 	depends on !NO_XIP_EARLY_STAGES
diff --git a/src/include/cpu/x86/mtrr.h b/src/include/cpu/x86/mtrr.h
index 412330449f..9227710596 100644
--- a/src/include/cpu/x86/mtrr.h
+++ b/src/include/cpu/x86/mtrr.h
@@ -190,10 +190,6 @@ static inline unsigned int fls(unsigned int x)
  */
 #define CACHE_TMP_RAMTOP (16<<20)
 
-#if ((CONFIG_XIP_ROM_SIZE & (CONFIG_XIP_ROM_SIZE - 1)) != 0)
-# error "CONFIG_XIP_ROM_SIZE is not a power of 2"
-#endif
-
 /* For ROM caching, generally, try to use the next power of 2. */
 #define OPTIMAL_CACHE_ROM_SIZE _ALIGN_UP_POW2(CONFIG_ROM_SIZE)
 #define OPTIMAL_CACHE_ROM_BASE _FROM_4G_TOP(OPTIMAL_CACHE_ROM_SIZE)