descriptor for chips
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@831 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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/* chips are arbitrary chips (superio, southbridge, etc.)
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* They have private structures that define chip resources and default
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* settings. They have four externally visible functions for control.
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* new settings are provided as ascii strings.
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*/
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/* some of the types of resources chips can control */
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struct com_ports {
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unsigned int enable,baud, base, irq;
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};
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/* lpt port description.
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* Note that for many chips you only really need to define the
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* enable.
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*/
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struct lpt_ports {
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unsigned int enable, // 1 if this port is enabled
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mode, // pp mode
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base, // IO base of the parallel port
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irq; // irq
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};
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/* linkages from devices of a type (e.g. superio devices)
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* to the actual physical PCI device. This type is used in an array of
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* structs built by NLBConfig.py. We owe this idea to Plan 9.
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*/
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struct chip;
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struct chip_control {
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void (*alloc)(struct chip *s);
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void (*pre_pci_init)(struct chip *s);
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void (*init)(struct chip *s);
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void (*finishup)(struct chip *s);
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char *path; /* the default path. Can be overridden
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* by commands in config
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*/
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// This is the print name for debugging
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char *name;
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};
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struct chip {
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struct chip_control *control; /* for this device */
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char *path; /* can be 0, in which case the default is taken */
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char *configuration; /* can be 0. */
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};
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