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mb/google/brya/var/marasov: Update MSR Package Power Limit-1 values 

As customer demand, it is necessary to set MSR Package Power Limit-1 to 17W for the DTT setting to optimize performance.

The PL1 value (17W) suggested by the thermal team which is different from the reference code(PL1=15W).

BUG=b:312321601
BRANCH=firmware-brya-14505.B
TEST=emerge-brya coreboot chromeos-bootimage
     Built and booted into OS, and confirm MSR PL1=17W correctly.

Change-Id: If7874d26038118c5605cf0721c30e681b45123fe
Signed-off-by: Daniel Peng <Daniel_Peng@pegatron.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79335
Reviewed-by: Eric Lai <ericllai@google.com>
Reviewed-by: Daniel Peng <daniel_peng@pegatron.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Daniel Peng 2023-11-29 14:46:05 +08:00 committed by Subrata Banik
parent 38ab95ba5a
commit 49d1cf9d49
1 changed files with 6 additions and 0 deletions
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6
src/mainboard/google/brya/variants/marasov/overridetree.cb
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@ -134,6 +134,12 @@ chip soc/intel/alderlake
register "tcc_offset" = "5" # TCC of 100 register "tcc_offset" = "5" # TCC of 100
register "power_limits_config[RPL_P_282_242_142_15W_CORE]" = "{
.tdp_pl1_override = 17,
.tdp_pl2_override = 55,
.tdp_pl4 = 114,
}"
device domain 0 on device domain 0 on
device ref igpu on device ref igpu on
chip drivers/gfx/generic chip drivers/gfx/generic