src/ec/google/chromeec: Get Type-C Mux info from EC (TCPM)
EC being the TCPM decides the mux configuration after negotiating with the port partner on the Type-C port. The APIs added here will give the current essential mux state information for a given port. BUG=None BRANCH=None TEST=Built coreboot image and verified that using this patch mux is being set for display during boot Change-Id: If994a459288ef31b0e6da8c6cdfd0ce3a0303981 Signed-off-by: Divya Sasidharan <divya.s.sasidharan@intel.com> Signed-off-by: Brandon Breitenstein <brandon.breitenstein@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42078 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
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@ -1380,11 +1380,11 @@ enum ec_image google_chromeec_get_current_image(void)
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return ec_image_type;
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}
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int google_chromeec_get_num_pd_ports(int *num_ports)
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int google_chromeec_get_num_pd_ports(unsigned int *num_ports)
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{
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struct ec_response_charge_port_count resp = {};
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struct chromeec_command cmd = {
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.cmd_code = EC_CMD_CHARGE_PORT_COUNT,
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.cmd_code = EC_CMD_USB_PD_PORTS,
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.cmd_version = 0,
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.cmd_data_out = &resp,
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.cmd_size_in = 0,
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@ -1441,6 +1441,65 @@ int google_ec_running_ro(void)
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return (google_chromeec_get_current_image() == EC_IMAGE_RO);
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}
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int google_chromeec_usb_pd_control(int port, bool *ufp, bool *dbg_acc, uint8_t *dp_mode)
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{
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struct ec_params_usb_pd_control pd_control = {
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.port = port,
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.role = USB_PD_CTRL_ROLE_NO_CHANGE,
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.mux = USB_PD_CTRL_ROLE_NO_CHANGE,
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.swap = USB_PD_CTRL_SWAP_NONE,
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};
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struct ec_response_usb_pd_control_v2 resp = {};
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struct chromeec_command cmd = {
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.cmd_code = EC_CMD_USB_PD_CONTROL,
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.cmd_version = 2,
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.cmd_data_in = &pd_control,
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.cmd_size_in = sizeof(pd_control),
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.cmd_data_out = &resp,
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.cmd_size_out = sizeof(resp),
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.cmd_dev_index = 0,
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};
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if (google_chromeec_command(&cmd) < 0)
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return -1;
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*ufp = (resp.cc_state == PD_CC_DFP_ATTACHED);
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*dbg_acc = (resp.cc_state == PD_CC_DFP_DEBUG_ACC);
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*dp_mode = resp.dp_mode;
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return 0;
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}
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/**
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* Check for the current mux state in EC. Flags representing the mux state found
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* in ec_commands.h
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*/
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int google_chromeec_usb_get_pd_mux_info(int port, uint8_t *flags)
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{
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struct ec_params_usb_pd_mux_info req_mux = {
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.port = port,
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};
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struct ec_response_usb_pd_mux_info resp_mux = {};
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struct chromeec_command cmd = {
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.cmd_code = EC_CMD_USB_PD_MUX_INFO,
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.cmd_version = 0,
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.cmd_data_in = &req_mux,
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.cmd_size_in = sizeof(req_mux),
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.cmd_data_out = &resp_mux,
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.cmd_size_out = sizeof(resp_mux),
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.cmd_dev_index = 0,
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};
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if (port < 0)
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return -1;
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if (google_chromeec_command(&cmd) < 0)
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return -1;
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*flags = resp_mux.flags;
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return 0;
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}
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/**
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* Check if EC/TCPM is in an alternate mode or not.
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*
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@ -27,6 +27,15 @@ int google_ec_running_ro(void);
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enum ec_image google_chromeec_get_current_image(void);
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void google_chromeec_init(void);
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int google_chromeec_pd_get_amode(uint16_t svid);
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/* Check for the current mux state in EC
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* in: int port physical port number of the type-c port
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* out: uint8_t flags flags representing the status of the mux such as
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* usb capability, dp capability, cable type, etc
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*/
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int google_chromeec_usb_get_pd_mux_info(int port, uint8_t *flags);
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/* Returns data role and type of device connected */
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int google_chromeec_usb_pd_control(int port, bool *ufp, bool *dbg_acc,
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uint8_t *dp_mode);
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int google_chromeec_wait_for_displayport(long timeout);
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/* Device events */
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@ -306,7 +315,7 @@ int google_chromeec_get_cmd_versions(int command, uint32_t *pmask);
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* of PD-capable USB ports according to the EC.
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* @return 0 on success, -1 on error
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*/
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int google_chromeec_get_num_pd_ports(int *num_ports);
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int google_chromeec_get_num_pd_ports(unsigned int *num_ports);
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/* Structure representing the capabilities of a USB-PD port */
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struct usb_pd_port_caps {
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@ -144,7 +144,8 @@ static bool match_connector(DEVTREE_CONST struct device *dev)
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static void fill_ssdt_typec_device(const struct device *dev)
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{
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int rv;
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int i, num_ports;
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int i;
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unsigned int num_ports;
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struct device *usb2_port;
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struct device *usb3_port;
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struct device *usb4_port;
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