mb/kontron/bsl6: Make use of the chipset devicetree

Use the references from the chipset devicetree as this makes the
comments superfluous and remove devices which are turned off.

Change-Id: Ic25d112a95903e77b58bda70bbcc3f08df383395
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79035
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
This commit is contained in:
Felix Singer 2023-11-12 17:43:45 +00:00 committed by Felix Singer
parent 13ee2e6d8a
commit 49dc2856d8
3 changed files with 24 additions and 29 deletions

View File

@ -66,10 +66,9 @@ chip soc/intel/skylake
device cpu_cluster 0 on end
device domain 0 on
device pci 00.0 on end # Host Bridge
device pci 02.0 on end # Integrated Graphics Device
device pci 08.0 on end # Gaussian Mixture Model
device pci 14.0 on # USB xHCI
device ref igpu on end
device ref gmm on end
device ref south_xhci on
register "usb2_ports" = "{
[0] = USB2_PORT_LONG(OC0),
[1] = USB2_PORT_LONG(OC0),
@ -78,9 +77,9 @@ chip soc/intel/skylake
[4] = USB2_PORT_LONG(OC2), /* Debug */
}"
end
device pci 14.2 on end # Thermal Subsystem
device pci 16.0 on end # Management Engine Interface 1
device pci 17.0 on # SATA
device ref thermal on end
device ref heci1 on end
device ref sata on
register "SataSalpSupport" = "1"
register "SataPortsEnable" = "{
[0] = 1,
@ -88,16 +87,16 @@ chip soc/intel/skylake
[2] = 1,
}"
end
device pci 1d.0 on # PCI Express Port 9 (COMe 0)
device ref pcie_rp9 on
register "PcieRpEnable[8]" = "1"
end
device pci 1d.1 on # PCI Express Port 10 (COMe 1)
device ref pcie_rp10 on
register "PcieRpEnable[9]" = "1"
end
device pci 1d.2 on # PCI Express Port 11 (COMe 2)
device ref pcie_rp11 on
register "PcieRpEnable[10]" = "1"
end
device pci 1f.0 on # LPC Interface
device ref lpc_espi on
register "serirq_mode" = "SERIRQ_CONTINUOUS"
# EC/kempld at 0xa80/0xa81
@ -111,14 +110,12 @@ chip soc/intel/skylake
device generic 0.0 on end # UART #0
end
end
device pci 1f.1 on end # P2SB
device pci 1f.2 on end # Power Management Controller
device pci 1f.4 on # SMBus
device ref smbus on
chip drivers/i2c/nct7802y
device i2c 0x2e on end
end
end
device pci 1f.5 on end # PCH SPI
device pci 1f.6 on end # GbE
device ref fast_spi on end
device ref gbe on end
end
end

View File

@ -5,7 +5,7 @@ chip soc/intel/skylake
register "SkipExtGfxScan" = "1"
device domain 0 on
device pci 1f.0 on
device ref lpc_espi on
chip ec/kontron/kempld
device generic 1.0 on # I2C
chip drivers/i2c/lm96000
@ -40,16 +40,14 @@ chip soc/intel/skylake
end
end
end
end # LPC Interface
device pci 1f.4 on
end
device ref smbus on
chip drivers/i2c/nct7802y
register "fan[1].mode" = "FAN_MANUAL"
register "fan[1].duty_cycle" = "100"
device i2c 0x2e on end
end
end # SMBus
device pci 1f.5 on end # PCH SPI
device pci 1f.6 on end # GbE # Debug
end
end
end

View File

@ -21,12 +21,12 @@ chip soc/intel/skylake
register "SataPortsEnable[3]" = "1"
device domain 0 on
device pci 1c.0 on end # PCI Express Port 1
device pci 1c.1 on end # PCI Express Port 2
device pci 1c.2 on end # PCI Express Port 3
device pci 1c.3 on end # PCI Express Port 4
device pci 1d.3 on end # PCI Express Port 12
device pci 1f.4 on
device ref pcie_rp1 on end
device ref pcie_rp2 on end
device ref pcie_rp3 on end
device ref pcie_rp4 on end
device ref pcie_rp12 on end
device ref smbus on
chip drivers/i2c/nct7802y
register "peci[0]" = "{ PECI_DOMAIN_0, 100 }"
register "fan[1].mode" = "FAN_SMART"
@ -40,6 +40,6 @@ chip soc/intel/skylake
device i2c 0x2e on end
end
end # SMBus
end
end
end