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soc/intel/broadwell: fix USBDEBUG copy-pasta 

The broadwell soc code was upstreamed based off an old coreboot branch
and apparently never tested with USBDEBUG.
This changeset fixes USBDEBUG on the not yet upstreamed Auron-Paine
board, as verified with a FT232H setup. The fix is simply removing
outdated code that since branching off had been deduplicated in upstream
coreboot, anyway.

Change-Id: I53c924aa2a5357ed8313d0c9eaa2f9f9e132345e
Signed-off-by: Georg Wicherski <gwicherski@gmail.com>
Reviewed-on: http://review.coreboot.org/11874
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
This commit is contained in:
Georg Wicherski 2015-10-13 16:27:15 +02:00 committed by Kyösti Mälkki
parent 615f69e53d
commit 49ee5efea7
4 changed files with 3 additions and 95 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

6
src/soc/intel/broadwell/Makefile.inc
View File

@ -66,12 +66,6 @@ smm-y += xhci.c
ramstage-srcs += src/mainboard/$(MAINBOARDDIR)/hda_verb.c
ifeq ($(CONFIG_USBDEBUG),y)
ramstage-y += usbdebug.c
romstage-y += usbdebug.c
smm-y += usbdebug.c
endif
cpu_microcode_bins += 3rdparty/blobs/soc/intel/broadwell/microcode.bin
CPPFLAGS_common += -Isrc/soc/intel/broadwell/include

14
src/soc/intel/broadwell/cpu.c
View File

@ -574,27 +574,13 @@ static void configure_mca(void)
wrmsr(IA32_MC0_STATUS + (i * 4), msr);
}
#if CONFIG_USBDEBUG
static unsigned ehci_debug_addr;
#endif
static void bsp_init_before_ap_bringup(struct bus *cpu_bus)
{
#if CONFIG_USBDEBUG
if(!ehci_debug_addr)
ehci_debug_addr = get_ehci_debug();
set_ehci_debug(0);
#endif
/* Setup MTRRs based on physical address size. */
x86_setup_fixed_mtrrs();
x86_setup_var_mtrrs(cpuid_eax(0x80000008) & 0xff, 2);
x86_mtrr_check();
#if CONFIG_USBDEBUG
set_ehci_debug(ehci_debug_addr);
#endif
initialize_vr_config();
calibrate_24mhz_bclk();
configure_pch_power_sharing();

27
src/soc/intel/broadwell/ehci.c
View File

@ -23,6 +23,7 @@
#include <device/device.h>
#include <device/pci.h>
#include <device/pci_ids.h>
#include <device/pci_ehci.h>
#include <arch/io.h>
#include <soc/ehci.h>
#include <soc/pch.h>
@ -48,28 +49,6 @@ static void usb_ehci_set_subsystem(device_t dev, unsigned vendor, unsigned devic
pci_write_config8(dev, 0x80, access_cntl);
}
static void usb_ehci_set_resources(struct device *dev)
{
#if CONFIG_USBDEBUG
struct resource *res;
u32 base;
u32 usb_debug;
usb_debug = get_ehci_debug();
set_ehci_debug(0);
#endif
pci_dev_set_resources(dev);
#if CONFIG_USBDEBUG
res = find_resource(dev, 0x10);
set_ehci_debug(usb_debug);
if (!res) return;
base = res->base;
set_ehci_base(base);
report_resource_stored(dev, res, "");
#endif
}
static void ehci_enable(struct device *dev)
{
if (CONFIG_USBDEBUG)
@ -83,8 +62,8 @@ static struct pci_operations ehci_ops_pci = {
};
static struct device_operations usb_ehci_ops = {
.read_resources = &pci_dev_read_resources,
.set_resources = &usb_ehci_set_resources,
.read_resources = &pci_ehci_read_resources,
.set_resources = &pci_dev_set_resources,
.enable_resources = &pci_dev_enable_resources,
.ops_pci = &ehci_ops_pci,
.enable = &ehci_enable,

51
src/soc/intel/broadwell/usbdebug.c
View File

@ -1,51 +0,0 @@
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2014 Google Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc.
*/
#include <stdint.h>
#include <arch/io.h>
#include <console/console.h>
#include <usbdebug.h>
#include <device/pci.h>
#include <device/pci_def.h>
#include <soc/pci_devs.h>
void set_debug_port(unsigned int port)
{
/* Hardcoded to physical port 1 */
}
void enable_usbdebug(unsigned int port)
{
u32 tmp32;
tmp32 = pci_read_config32(PCH_DEV_EHCI, PCI_VENDOR_ID);
if (tmp32 == 0xffffffff || tmp32 == 0)
return;
/* Set the EHCI BAR address. */
pci_write_config32(PCH_DEV_EHCI, EHCI_BAR_INDEX, CONFIG_EHCI_BAR);
/* Enable access to the EHCI memory space registers. */
pci_write_config8(PCH_DEV_EHCI, PCI_COMMAND, PCI_COMMAND_MEMORY);
/* Force ownership of the Debug Port to the EHCI controller. */
tmp32 = read32(CONFIG_EHCI_BAR + CONFIG_EHCI_DEBUG_OFFSET);
tmp32 |= (1 << 30);
write32(CONFIG_EHCI_BAR + CONFIG_EHCI_DEBUG_OFFSET, tmp32);
}