soc/intel/broadwell: fix USBDEBUG copy-pasta
The broadwell soc code was upstreamed based off an old coreboot branch and apparently never tested with USBDEBUG. This changeset fixes USBDEBUG on the not yet upstreamed Auron-Paine board, as verified with a FT232H setup. The fix is simply removing outdated code that since branching off had been deduplicated in upstream coreboot, anyway. Change-Id: I53c924aa2a5357ed8313d0c9eaa2f9f9e132345e Signed-off-by: Georg Wicherski <gwicherski@gmail.com> Reviewed-on: http://review.coreboot.org/11874 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
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src/soc/intel/broadwell
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@ -66,12 +66,6 @@ smm-y += xhci.c
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ramstage-srcs += src/mainboard/$(MAINBOARDDIR)/hda_verb.c
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ramstage-srcs += src/mainboard/$(MAINBOARDDIR)/hda_verb.c
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ifeq ($(CONFIG_USBDEBUG),y)
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ramstage-y += usbdebug.c
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romstage-y += usbdebug.c
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smm-y += usbdebug.c
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endif
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cpu_microcode_bins += 3rdparty/blobs/soc/intel/broadwell/microcode.bin
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cpu_microcode_bins += 3rdparty/blobs/soc/intel/broadwell/microcode.bin
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CPPFLAGS_common += -Isrc/soc/intel/broadwell/include
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CPPFLAGS_common += -Isrc/soc/intel/broadwell/include
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@ -574,27 +574,13 @@ static void configure_mca(void)
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wrmsr(IA32_MC0_STATUS + (i * 4), msr);
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wrmsr(IA32_MC0_STATUS + (i * 4), msr);
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}
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}
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#if CONFIG_USBDEBUG
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static unsigned ehci_debug_addr;
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#endif
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static void bsp_init_before_ap_bringup(struct bus *cpu_bus)
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static void bsp_init_before_ap_bringup(struct bus *cpu_bus)
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{
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{
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#if CONFIG_USBDEBUG
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if(!ehci_debug_addr)
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ehci_debug_addr = get_ehci_debug();
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set_ehci_debug(0);
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#endif
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/* Setup MTRRs based on physical address size. */
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/* Setup MTRRs based on physical address size. */
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x86_setup_fixed_mtrrs();
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x86_setup_fixed_mtrrs();
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x86_setup_var_mtrrs(cpuid_eax(0x80000008) & 0xff, 2);
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x86_setup_var_mtrrs(cpuid_eax(0x80000008) & 0xff, 2);
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x86_mtrr_check();
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x86_mtrr_check();
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#if CONFIG_USBDEBUG
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set_ehci_debug(ehci_debug_addr);
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#endif
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initialize_vr_config();
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initialize_vr_config();
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calibrate_24mhz_bclk();
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calibrate_24mhz_bclk();
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configure_pch_power_sharing();
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configure_pch_power_sharing();
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@ -23,6 +23,7 @@
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#include <device/device.h>
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#include <device/device.h>
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#include <device/pci.h>
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#include <device/pci.h>
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#include <device/pci_ids.h>
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#include <device/pci_ids.h>
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#include <device/pci_ehci.h>
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#include <arch/io.h>
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#include <arch/io.h>
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#include <soc/ehci.h>
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#include <soc/ehci.h>
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#include <soc/pch.h>
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#include <soc/pch.h>
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@ -48,28 +49,6 @@ static void usb_ehci_set_subsystem(device_t dev, unsigned vendor, unsigned devic
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pci_write_config8(dev, 0x80, access_cntl);
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pci_write_config8(dev, 0x80, access_cntl);
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}
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}
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static void usb_ehci_set_resources(struct device *dev)
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{
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#if CONFIG_USBDEBUG
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struct resource *res;
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u32 base;
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u32 usb_debug;
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usb_debug = get_ehci_debug();
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set_ehci_debug(0);
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#endif
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pci_dev_set_resources(dev);
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#if CONFIG_USBDEBUG
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res = find_resource(dev, 0x10);
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set_ehci_debug(usb_debug);
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if (!res) return;
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base = res->base;
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set_ehci_base(base);
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report_resource_stored(dev, res, "");
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#endif
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}
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static void ehci_enable(struct device *dev)
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static void ehci_enable(struct device *dev)
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{
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{
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if (CONFIG_USBDEBUG)
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if (CONFIG_USBDEBUG)
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@ -83,8 +62,8 @@ static struct pci_operations ehci_ops_pci = {
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};
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};
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static struct device_operations usb_ehci_ops = {
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static struct device_operations usb_ehci_ops = {
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.read_resources = &pci_dev_read_resources,
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.read_resources = &pci_ehci_read_resources,
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.set_resources = &usb_ehci_set_resources,
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.set_resources = &pci_dev_set_resources,
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.enable_resources = &pci_dev_enable_resources,
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.enable_resources = &pci_dev_enable_resources,
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.ops_pci = &ehci_ops_pci,
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.ops_pci = &ehci_ops_pci,
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.enable = &ehci_enable,
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.enable = &ehci_enable,
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@ -1,51 +0,0 @@
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/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2014 Google Inc.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc.
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*/
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#include <stdint.h>
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#include <arch/io.h>
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#include <console/console.h>
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#include <usbdebug.h>
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#include <device/pci.h>
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#include <device/pci_def.h>
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#include <soc/pci_devs.h>
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void set_debug_port(unsigned int port)
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{
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/* Hardcoded to physical port 1 */
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}
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void enable_usbdebug(unsigned int port)
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{
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u32 tmp32;
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tmp32 = pci_read_config32(PCH_DEV_EHCI, PCI_VENDOR_ID);
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if (tmp32 == 0xffffffff || tmp32 == 0)
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return;
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/* Set the EHCI BAR address. */
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pci_write_config32(PCH_DEV_EHCI, EHCI_BAR_INDEX, CONFIG_EHCI_BAR);
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/* Enable access to the EHCI memory space registers. */
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pci_write_config8(PCH_DEV_EHCI, PCI_COMMAND, PCI_COMMAND_MEMORY);
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/* Force ownership of the Debug Port to the EHCI controller. */
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tmp32 = read32(CONFIG_EHCI_BAR + CONFIG_EHCI_DEBUG_OFFSET);
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tmp32 |= (1 << 30);
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write32(CONFIG_EHCI_BAR + CONFIG_EHCI_DEBUG_OFFSET, tmp32);
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}
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