diff --git a/src/southbridge/amd/agesa/hudson/bootblock.c b/src/southbridge/amd/agesa/hudson/bootblock.c
index e103bc4325..e8307b1c07 100644
--- a/src/southbridge/amd/agesa/hudson/bootblock.c
+++ b/src/southbridge/amd/agesa/hudson/bootblock.c
@@ -19,9 +19,7 @@
 static void hudson_enable_rom(void)
 {
 	u8 reg8;
-	pci_devfn_t dev;
-
-	dev = PCI_DEV(0, 0x14, 3);
+	const pci_devfn_t dev = PCI_DEV(0, 0x14, 3);
 
 	/* Decode variable LPC ROM address ranges 1 and 2. */
 	reg8 = pci_s_read_config8(dev, 0x48);
@@ -49,7 +47,6 @@ static void hudson_enable_rom(void)
 
 void bootblock_early_southbridge_init(void)
 {
-	pci_devfn_t dev;
 	u32 data;
 
 	hudson_enable_rom();
@@ -61,7 +58,7 @@ void bootblock_early_southbridge_init(void)
 	else if (CONFIG(POST_DEVICE_LPC))
 		hudson_lpc_port80();
 
-	dev = PCI_DEV(0, 0x14, 3);
+	const pci_devfn_t dev = PCI_DEV(0, 0x14, 3);
 	data = pci_read_config32(dev, LPC_IO_OR_MEM_DECODE_ENABLE);
 	/* enable 0x2e/0x4e IO decoding for SuperIO */
 	pci_write_config32(dev, LPC_IO_OR_MEM_DECODE_ENABLE, data | 3);
diff --git a/src/southbridge/amd/agesa/hudson/early_setup.c b/src/southbridge/amd/agesa/hudson/early_setup.c
index a4399c9b2d..ed2b18eaf2 100644
--- a/src/southbridge/amd/agesa/hudson/early_setup.c
+++ b/src/southbridge/amd/agesa/hudson/early_setup.c
@@ -60,10 +60,9 @@ void hudson_pci_port80(void)
 void hudson_lpc_port80(void)
 {
 	u8 byte;
-	pci_devfn_t dev;
 
 	/* Enable port 80 LPC decode in pci function 3 configuration space. */
-	dev = PCI_DEV(0, 0x14, 3);
+	const pci_devfn_t dev = PCI_DEV(0, 0x14, 3);
 	byte = pci_read_config8(dev, 0x4a);
 	byte |= 1 << 5; /* enable port 80 */
 	pci_write_config8(dev, 0x4a, byte);
@@ -71,13 +70,12 @@ void hudson_lpc_port80(void)
 
 void hudson_lpc_decode(void)
 {
-	pci_devfn_t dev;
 	u32 tmp;
 
 	/* Enable LPC controller */
 	pm_write8(0xec, pm_read8(0xec) | 0x01);
 
-	dev = PCI_DEV(0, 0x14, 3);
+	const pci_devfn_t dev = PCI_DEV(0, 0x14, 3);
 	/* Serial port enumeration on Hudson:
 	 * PORT0 - 0x3f8
 	 * PORT1 - 0x2f8