AGESA fam14: Add amd_initenv()
Not part of wrapper to AGESA, but workaround for enable_resources(). Also remove remains of comments in non-fam14 wrappers. Change-Id: I2526821ca283feb6a506b602b86f817f8b03b341 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/7816 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
This commit is contained in:
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48518f0d60
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4a08e15086
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@ -97,3 +97,83 @@ void amd_initmmio(void)
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PciData = (AMD_APU_SSID << 0x10) | AMD_APU_SVID;
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PciData = (AMD_APU_SSID << 0x10) | AMD_APU_SVID;
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LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
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LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
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}
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}
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void amd_initenv(void)
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{
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AMD_INTERFACE_PARAMS AmdParamStruct;
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PCI_ADDR PciAddress;
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UINT32 PciValue;
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/* Initialize Subordinate Bus Number and Secondary Bus Number
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* In platform BIOS this address is allocated by PCI enumeration code
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Modify D1F0x18
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*/
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PciAddress.Address.Bus = 0;
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PciAddress.Address.Device = 1;
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PciAddress.Address.Function = 0;
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PciAddress.Address.Register = 0x18;
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/* Write to D1F0x18 */
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LibAmdPciRead(AccessWidth32, PciAddress, &PciValue, &AmdParamStruct.StdHeader);
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PciValue |= 0x00010100;
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LibAmdPciWrite(AccessWidth32, PciAddress, &PciValue, &AmdParamStruct.StdHeader);
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/* Initialize GMM Base Address for Legacy Bridge Mode
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* Modify B1D5F0x18
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*/
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PciAddress.Address.Bus = 1;
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PciAddress.Address.Device = 5;
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PciAddress.Address.Function = 0;
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PciAddress.Address.Register = 0x18;
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LibAmdPciRead(AccessWidth32, PciAddress, &PciValue, &AmdParamStruct.StdHeader);
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PciValue |= 0x96000000;
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LibAmdPciWrite(AccessWidth32, PciAddress, &PciValue, &AmdParamStruct.StdHeader);
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/* Initialize FB Base Address for Legacy Bridge Mode
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* Modify B1D5F0x10
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*/
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PciAddress.Address.Register = 0x10;
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LibAmdPciRead(AccessWidth32, PciAddress, &PciValue, &AmdParamStruct.StdHeader);
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PciValue |= 0x80000000;
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LibAmdPciWrite(AccessWidth32, PciAddress, &PciValue, &AmdParamStruct.StdHeader);
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/* Initialize GMM Base Address for Pcie Mode
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* Modify B0D1F0x18
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*/
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PciAddress.Address.Bus = 0;
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PciAddress.Address.Device = 1;
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PciAddress.Address.Function = 0;
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PciAddress.Address.Register = 0x18;
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LibAmdPciRead(AccessWidth32, PciAddress, &PciValue, &AmdParamStruct.StdHeader);
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PciValue |= 0x96000000;
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LibAmdPciWrite(AccessWidth32, PciAddress, &PciValue, &AmdParamStruct.StdHeader);
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/* Initialize FB Base Address for Pcie Mode
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* Modify B0D1F0x10
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*/
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PciAddress.Address.Register = 0x10;
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LibAmdPciRead(AccessWidth32, PciAddress, &PciValue, &AmdParamStruct.StdHeader);
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PciValue |= 0x80000000;
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LibAmdPciWrite(AccessWidth32, PciAddress, &PciValue, &AmdParamStruct.StdHeader);
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/* Initialize MMIO Base and Limit Address
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* Modify B0D1F0x20
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*/
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PciAddress.Address.Bus = 0;
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PciAddress.Address.Device = 1;
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PciAddress.Address.Function = 0;
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PciAddress.Address.Register = 0x20;
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LibAmdPciRead(AccessWidth32, PciAddress, &PciValue, &AmdParamStruct.StdHeader);
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PciValue |= 0x96009600;
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LibAmdPciWrite(AccessWidth32, PciAddress, &PciValue, &AmdParamStruct.StdHeader);
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/* Initialize MMIO Prefetchable Memory Limit and Base
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* Modify B0D1F0x24
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*/
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PciAddress.Address.Register = 0x24;
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LibAmdPciRead(AccessWidth32, PciAddress, &PciValue, &AmdParamStruct.StdHeader);
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PciValue |= 0x8FF18001;
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LibAmdPciWrite(AccessWidth32, PciAddress, &PciValue, &AmdParamStruct.StdHeader);
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}
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@ -86,6 +86,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
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post_code(0x41);
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post_code(0x41);
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agesawrapper_amdinitenv();
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agesawrapper_amdinitenv();
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amd_initenv();
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post_code(0x50);
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post_code(0x50);
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copy_and_run();
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copy_and_run();
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@ -93,6 +93,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
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post_code(0x42);
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post_code(0x42);
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agesawrapper_amdinitenv();
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agesawrapper_amdinitenv();
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amd_initenv();
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} else { /* S3 detect */
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} else { /* S3 detect */
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printk(BIOS_INFO, "S3 detected\n");
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printk(BIOS_INFO, "S3 detected\n");
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@ -86,6 +86,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
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post_code(0x41);
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post_code(0x41);
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agesawrapper_amdinitenv();
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agesawrapper_amdinitenv();
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amd_initenv();
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post_code(0x50);
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post_code(0x50);
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copy_and_run();
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copy_and_run();
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@ -80,6 +80,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
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post_code(0x41);
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post_code(0x41);
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agesawrapper_amdinitenv();
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agesawrapper_amdinitenv();
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amd_initenv();
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post_code(0x50);
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post_code(0x50);
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copy_and_run();
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copy_and_run();
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@ -86,6 +86,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
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post_code(0x41);
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post_code(0x41);
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agesawrapper_amdinitenv();
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agesawrapper_amdinitenv();
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amd_initenv();
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post_code(0x50);
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post_code(0x50);
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copy_and_run();
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copy_and_run();
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@ -101,6 +101,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
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post_code(0x42);
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post_code(0x42);
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agesawrapper_amdinitenv();
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agesawrapper_amdinitenv();
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amd_initenv();
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} else { /* S3 detect */
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} else { /* S3 detect */
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printk(BIOS_INFO, "S3 detected\n");
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printk(BIOS_INFO, "S3 detected\n");
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@ -109,6 +109,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
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post_code(0x42);
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post_code(0x42);
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agesawrapper_amdinitenv();
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agesawrapper_amdinitenv();
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amd_initenv();
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} else { /* S3 detect */
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} else { /* S3 detect */
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printk(BIOS_INFO, "S3 detected\n");
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printk(BIOS_INFO, "S3 detected\n");
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@ -96,6 +96,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
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post_code(0x42);
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post_code(0x42);
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agesawrapper_amdinitenv();
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agesawrapper_amdinitenv();
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amd_initenv();
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} else { /* S3 detect */
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} else { /* S3 detect */
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printk(BIOS_INFO, "S3 detected\n");
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printk(BIOS_INFO, "S3 detected\n");
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@ -97,6 +97,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
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post_code(0x42);
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post_code(0x42);
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agesawrapper_amdinitenv();
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agesawrapper_amdinitenv();
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amd_initenv();
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} else { /* S3 detect */
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} else { /* S3 detect */
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printk(BIOS_INFO, "S3 detected\n");
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printk(BIOS_INFO, "S3 detected\n");
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@ -48,6 +48,7 @@ void agesawrapper_trace(AGESA_STATUS ret, AMD_CONFIG_PARAMS *StdHeader, const ch
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void amd_initcpuio(void);
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void amd_initcpuio(void);
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void amd_initmmio(void);
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void amd_initmmio(void);
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void amd_initenv(void);
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AGESA_STATUS agesawrapper_amdinitresume(void);
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AGESA_STATUS agesawrapper_amdinitresume(void);
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AGESA_STATUS agesawrapper_amdS3Save(void);
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AGESA_STATUS agesawrapper_amdS3Save(void);
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@ -125,8 +125,6 @@ AGESA_STATUS agesawrapper_amdinitenv(VOID)
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{
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{
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AGESA_STATUS status;
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AGESA_STATUS status;
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AMD_INTERFACE_PARAMS AmdParamStruct;
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AMD_INTERFACE_PARAMS AmdParamStruct;
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PCI_ADDR PciAddress;
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UINT32 PciValue;
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memset(&AmdParamStruct, 0, sizeof(AMD_INTERFACE_PARAMS));
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memset(&AmdParamStruct, 0, sizeof(AMD_INTERFACE_PARAMS));
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@ -141,80 +139,7 @@ AGESA_STATUS agesawrapper_amdinitenv(VOID)
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status = AmdInitEnv((AMD_ENV_PARAMS *) AmdParamStruct.NewStructPtr);
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status = AmdInitEnv((AMD_ENV_PARAMS *) AmdParamStruct.NewStructPtr);
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AGESA_EVENTLOG(status, &AmdParamStruct.StdHeader);
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AGESA_EVENTLOG(status, &AmdParamStruct.StdHeader);
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/* Initialize Subordinate Bus Number and Secondary Bus Number
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* In platform BIOS this address is allocated by PCI enumeration code
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Modify D1F0x18
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*/
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PciAddress.Address.Bus = 0;
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PciAddress.Address.Device = 1;
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PciAddress.Address.Function = 0;
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PciAddress.Address.Register = 0x18;
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/* Write to D1F0x18 */
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LibAmdPciRead(AccessWidth32, PciAddress, &PciValue, &AmdParamStruct.StdHeader);
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PciValue |= 0x00010100;
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LibAmdPciWrite(AccessWidth32, PciAddress, &PciValue, &AmdParamStruct.StdHeader);
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/* Initialize GMM Base Address for Legacy Bridge Mode
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* Modify B1D5F0x18
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*/
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PciAddress.Address.Bus = 1;
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PciAddress.Address.Device = 5;
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PciAddress.Address.Function = 0;
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PciAddress.Address.Register = 0x18;
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LibAmdPciRead(AccessWidth32, PciAddress, &PciValue, &AmdParamStruct.StdHeader);
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PciValue |= 0x96000000;
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LibAmdPciWrite(AccessWidth32, PciAddress, &PciValue, &AmdParamStruct.StdHeader);
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/* Initialize FB Base Address for Legacy Bridge Mode
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* Modify B1D5F0x10
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*/
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PciAddress.Address.Register = 0x10;
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LibAmdPciRead(AccessWidth32, PciAddress, &PciValue, &AmdParamStruct.StdHeader);
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PciValue |= 0x80000000;
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LibAmdPciWrite(AccessWidth32, PciAddress, &PciValue, &AmdParamStruct.StdHeader);
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/* Initialize GMM Base Address for Pcie Mode
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* Modify B0D1F0x18
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*/
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PciAddress.Address.Bus = 0;
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PciAddress.Address.Device = 1;
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PciAddress.Address.Function = 0;
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PciAddress.Address.Register = 0x18;
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LibAmdPciRead(AccessWidth32, PciAddress, &PciValue, &AmdParamStruct.StdHeader);
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PciValue |= 0x96000000;
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LibAmdPciWrite(AccessWidth32, PciAddress, &PciValue, &AmdParamStruct.StdHeader);
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/* Initialize FB Base Address for Pcie Mode
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* Modify B0D1F0x10
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*/
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PciAddress.Address.Register = 0x10;
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LibAmdPciRead(AccessWidth32, PciAddress, &PciValue, &AmdParamStruct.StdHeader);
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PciValue |= 0x80000000;
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LibAmdPciWrite(AccessWidth32, PciAddress, &PciValue, &AmdParamStruct.StdHeader);
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/* Initialize MMIO Base and Limit Address
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* Modify B0D1F0x20
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*/
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PciAddress.Address.Bus = 0;
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PciAddress.Address.Device = 1;
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PciAddress.Address.Function = 0;
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PciAddress.Address.Register = 0x20;
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LibAmdPciRead(AccessWidth32, PciAddress, &PciValue, &AmdParamStruct.StdHeader);
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PciValue |= 0x96009600;
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LibAmdPciWrite(AccessWidth32, PciAddress, &PciValue, &AmdParamStruct.StdHeader);
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/* Initialize MMIO Prefetchable Memory Limit and Base
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* Modify B0D1F0x24
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*/
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PciAddress.Address.Register = 0x24;
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LibAmdPciRead(AccessWidth32, PciAddress, &PciValue, &AmdParamStruct.StdHeader);
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PciValue |= 0x8FF18001;
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LibAmdPciWrite(AccessWidth32, PciAddress, &PciValue, &AmdParamStruct.StdHeader);
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AmdReleaseStruct(&AmdParamStruct);
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AmdReleaseStruct(&AmdParamStruct);
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return status;
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return status;
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}
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}
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@ -150,10 +150,6 @@ AGESA_STATUS agesawrapper_amdinitenv(void)
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status = AmdInitEnv(EnvParam);
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status = AmdInitEnv(EnvParam);
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AGESA_EVENTLOG(status, &EnvParam->StdHeader);
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AGESA_EVENTLOG(status, &EnvParam->StdHeader);
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/* Initialize Subordinate Bus Number and Secondary Bus Number
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* In platform BIOS this address is allocated by PCI enumeration code
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Modify D1F0x18
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*/
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return status;
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return status;
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}
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}
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@ -150,10 +150,6 @@ AGESA_STATUS agesawrapper_amdinitenv(void)
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status = AmdInitEnv(EnvParam);
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status = AmdInitEnv(EnvParam);
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AGESA_EVENTLOG(status, &EnvParam->StdHeader);
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AGESA_EVENTLOG(status, &EnvParam->StdHeader);
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/* Initialize Subordinate Bus Number and Secondary Bus Number
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* In platform BIOS this address is allocated by PCI enumeration code
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Modify D1F0x18
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*/
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return status;
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return status;
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}
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}
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@ -150,10 +150,6 @@ AGESA_STATUS agesawrapper_amdinitenv(void)
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status = AmdInitEnv(EnvParam);
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status = AmdInitEnv(EnvParam);
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AGESA_EVENTLOG(status, &EnvParam->StdHeader);
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AGESA_EVENTLOG(status, &EnvParam->StdHeader);
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/* Initialize Subordinate Bus Number and Secondary Bus Number
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* In platform BIOS this address is allocated by PCI enumeration code
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Modify D1F0x18
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*/
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return status;
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return status;
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}
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}
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