GNUBoot
/
coreboot-kgpe-d16
2
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

mb/google/skyrim: Enable PCIe RTD3 support 

Add PCIe RTD3 support for Skyrim

BUG=b:245550573
TEST=Boot/Reboot cycles and Suspend_stress_test 10 times

Signed-off-by: JasonNien <finaljason@gmail.com>
Change-Id: I7f01827613eea2f254bc42c7f5aebeeb969b163a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70740
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
This commit is contained in:
JasonNien 2022-12-13 13:35:53 -06:00 committed by Felix Held
parent 267edecccb
commit 4a0e5e4741
3 changed files with 10 additions and 3 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

1
src/mainboard/google/skyrim/Kconfig
View File

@ -23,6 +23,7 @@ config BOARD_SPECIFIC_OPTIONS
select DRIVERS_I2C_NAU8825 select DRIVERS_I2C_NAU8825
select DRIVERS_USB_HUB select DRIVERS_USB_HUB
select DRIVERS_UART_ACPI select DRIVERS_UART_ACPI
select DRIVERS_PCIE_RTD3_DEVICE
select DRIVERS_PCIE_GENERIC select DRIVERS_PCIE_GENERIC
select EC_GOOGLE_CHROMEEC select EC_GOOGLE_CHROMEEC
select EC_GOOGLE_CHROMEEC_ESPI select EC_GOOGLE_CHROMEEC_ESPI

4
src/mainboard/google/skyrim/port_descriptors.c
View File

@ -28,7 +28,7 @@ static const fsp_dxio_descriptor skyrim_mdn_dxio_descriptors[] = {
.function_number = PCI_FUNC(SD_DEVFN), .function_number = PCI_FUNC(SD_DEVFN),
.link_speed_capability = GEN3, .link_speed_capability = GEN3,
.turn_off_unused_lanes = true, .turn_off_unused_lanes = true,
.link_aspm = ASPM_DISABLED, // TODO: switch to ASPM_L1 after b:245550573 .link_aspm = ASPM_L1,
.link_hotplug = 3, .link_hotplug = 3,
.gpio_group_id = GPIO_27, .gpio_group_id = GPIO_27,
.clk_req = CLK_REQ1, .clk_req = CLK_REQ1,
@ -42,7 +42,7 @@ static const fsp_dxio_descriptor skyrim_mdn_dxio_descriptors[] = {
.function_number = PCI_FUNC(NVME_DEVFN), .function_number = PCI_FUNC(NVME_DEVFN),
.link_speed_capability = GEN3, .link_speed_capability = GEN3,
.turn_off_unused_lanes = true, .turn_off_unused_lanes = true,
.link_aspm = ASPM_DISABLED, // TODO: switch to ASPM_L1 after b:245550573 .link_aspm = ASPM_L1,
.link_hotplug = 3, .link_hotplug = 3,
.gpio_group_id = GPIO_6, .gpio_group_id = GPIO_6,
.clk_req = CLK_REQ0, .clk_req = CLK_REQ0,

8
src/mainboard/google/skyrim/variants/baseboard/devicetree.cb
View File

@ -99,7 +99,13 @@ chip soc/amd/mendocino
end end
device ref iommu on end device ref iommu on end
device ref gpp_bridge_1 on end # SD device ref gpp_bridge_1 on end # SD
device ref gpp_bridge_2 on end # NVMe device ref gpp_bridge_2 on
# Required so the NVMe gets placed into D3 when entering S0i3.
chip drivers/pcie/rtd3/device
register "name" = ""NVME""
device pci 00.0 on end
end
end # NVMe
device ref gpp_bridge_a on # Internal GPP Bridge 0 to Bus A device ref gpp_bridge_a on # Internal GPP Bridge 0 to Bus A
device ref gfx on end # Internal GPU (GFX) device ref gfx on end # Internal GPU (GFX)