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{northbridge, soc, southbridge}/intel: Make use of pci_dev_set_subsystem() 

This patch removes local definitions of sub_system function and make use
of common function pci_dev_set_subsystem().

Change-Id: I91982597fdf586ab514bec3d8e4d09f2565fe56d
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/31982
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: David Guckian
Reviewed-by: Furquan Shaikh <furquan@google.com>
This commit is contained in:
Subrata Banik 2019-03-20 14:29:47 +05:30 committed by Patrick Georgi
parent 6520ec0650
commit 4a0f07166f
69 changed files with 75 additions and 839 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

9
src/device/pci_device.c
View File

@ -734,8 +734,13 @@ void pci_bus_reset(struct bus *bus)
void pci_dev_set_subsystem(struct device *dev, unsigned int vendor,
unsigned int device)
{
pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID,
((device & 0xffff) << 16) | (vendor & 0xffff));
if (!vendor || !device) {
pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID,
pci_read_config32(dev, PCI_VENDOR_ID));
} else {
pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID,
((device & 0xffff) << 16) | (vendor & 0xffff));
}
}
static int should_run_oprom(struct device *dev)

9
src/northbridge/intel/e7505/northbridge.c
View File

@ -74,15 +74,8 @@ static void mch_domain_set_resources(struct device *dev)
assign_resources(dev->link_list);
}
static void intel_set_subsystem(struct device *dev, unsigned int vendor,
unsigned int device)
{
pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID,
((device & 0xffff) << 16) | (vendor & 0xffff));
}
static struct pci_operations intel_pci_ops = {
.set_subsystem = intel_set_subsystem,
.set_subsystem = pci_dev_set_subsystem,
};
static struct device_operations pci_domain_ops = {

14
src/northbridge/intel/fsp_rangeley/northbridge.c
View File

@ -172,18 +172,6 @@ static void mc_set_resources(struct device *dev)
pci_dev_set_resources(dev);
}
static void intel_set_subsystem(struct device *dev, unsigned int vendor,
unsigned int device)
{
if (!vendor || !device) {
pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID,
pci_read_config32(dev, PCI_VENDOR_ID));
} else {
pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID,
((device & 0xffff) << 16) | (vendor & 0xffff));
}
}
static void northbridge_init(struct device *dev)
{
}
@ -193,7 +181,7 @@ static void northbridge_enable(struct device *dev)
}
static struct pci_operations intel_pci_ops = {
.set_subsystem = intel_set_subsystem,
.set_subsystem = pci_dev_set_subsystem,
};
static struct device_operations pci_domain_ops = {

15
src/northbridge/intel/gm45/gma.c
View File

@ -221,19 +221,6 @@ static void gma_func0_init(struct device *dev)
intel_gma_restore_opregion();
}
static void gma_set_subsystem(struct device *dev, unsigned int vendor,
unsigned int device)
{
if (!vendor || !device) {
pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID,
pci_read_config32(dev, PCI_VENDOR_ID));
} else {
pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID,
((device & 0xffff) << 16) | (vendor &
0xffff));
}
}
const struct i915_gpu_controller_info *
intel_gma_get_controller_info(void)
{
@ -287,7 +274,7 @@ static const char *gma_acpi_name(const struct device *dev)
}
static struct pci_operations gma_pci_ops = {
.set_subsystem = gma_set_subsystem,
.set_subsystem = pci_dev_set_subsystem,
};
static struct device_operations gma_func0_ops = {

14
src/northbridge/intel/haswell/gma.c
View File

@ -499,18 +499,6 @@ static void gma_func0_init(struct device *dev)
intel_gma_restore_opregion();
}
static void gma_set_subsystem(struct device *dev, unsigned int vendor,
unsigned int device)
{
if (!vendor || !device) {
pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID,
pci_read_config32(dev, PCI_VENDOR_ID));
} else {
pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID,
((device & 0xffff) << 16) | (vendor & 0xffff));
}
}
const struct i915_gpu_controller_info *
intel_gma_get_controller_info(void)
{
@ -558,7 +546,7 @@ gma_write_acpi_tables(struct device *const dev, unsigned long current,
}
static struct pci_operations gma_pci_ops = {
.set_subsystem = gma_set_subsystem,
.set_subsystem = pci_dev_set_subsystem,
};
static struct device_operations gma_func0_ops = {

14
src/northbridge/intel/haswell/minihd.c
View File

@ -103,20 +103,8 @@ static void minihd_init(struct device *dev)
}
}
static void minihd_set_subsystem(struct device *dev, unsigned int vendor,
unsigned int device)
{
if (!vendor || !device) {
pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID,
pci_read_config32(dev, PCI_VENDOR_ID));
} else {
pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID,
((device & 0xffff) << 16) | (vendor & 0xffff));
}
}
static struct pci_operations minihd_pci_ops = {
.set_subsystem = minihd_set_subsystem,
.set_subsystem = pci_dev_set_subsystem,
};
static struct device_operations minihd_ops = {

14
src/northbridge/intel/haswell/northbridge.c
View File

@ -468,18 +468,6 @@ static void disable_devices(void)
pci_write_config32(host_dev, DEVEN, deven);
}
static void intel_set_subsystem(struct device *dev, unsigned int vendor,
unsigned int device)
{
if (!vendor || !device) {
pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID,
pci_read_config32(dev, PCI_VENDOR_ID));
} else {
pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID,
((device & 0xffff) << 16) | (vendor & 0xffff));
}
}
static void northbridge_init(struct device *dev)
{
u8 bios_reset_cpl, pair;
@ -510,7 +498,7 @@ static void northbridge_init(struct device *dev)
}
static struct pci_operations intel_pci_ops = {
.set_subsystem = intel_set_subsystem,
.set_subsystem = pci_dev_set_subsystem,
};
static struct device_operations mc_ops = {

14
src/northbridge/intel/i945/gma.c
View File

@ -756,18 +756,6 @@ static void gma_func1_init(struct device *dev)
pci_write_config8(dev, 0xf4, 0xff);
}
static void gma_set_subsystem(struct device *dev, unsigned int vendor,
unsigned int device)
{
if (!vendor || !device) {
pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID,
pci_read_config32(dev, PCI_VENDOR_ID));
} else {
pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID,
((device & 0xffff) << 16) | (vendor & 0xffff));
}
}
const struct i915_gpu_controller_info *
intel_gma_get_controller_info(void)
{
@ -834,7 +822,7 @@ static const char *gma_acpi_name(const struct device *dev)
}
static struct pci_operations gma_pci_ops = {
.set_subsystem = gma_set_subsystem,
.set_subsystem = pci_dev_set_subsystem,
};
static struct device_operations gma_func0_ops = {

13
src/northbridge/intel/i945/northbridge.c
View File

@ -191,19 +191,8 @@ static void mc_read_resources(struct device *dev)
}
}
static void intel_set_subsystem(struct device *dev, unsigned int vendor,
unsigned int device)
{
if (!vendor || !device) {
pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID,
pci_read_config32(dev, PCI_VENDOR_ID));
} else {
pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID,
((device & 0xffff) << 16) | (vendor & 0xffff));
}
}
static struct pci_operations intel_pci_ops = {
.set_subsystem = intel_set_subsystem,
.set_subsystem = pci_dev_set_subsystem,
};
static struct device_operations mc_ops = {

15
src/northbridge/intel/nehalem/gma.c
View File

@ -623,19 +623,6 @@ static void gma_func0_init(struct device *dev)
intel_gma_restore_opregion();
}
static void gma_set_subsystem(struct device *dev, unsigned int vendor,
unsigned int device)
{
if (!vendor || !device) {
pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID,
pci_read_config32(dev, PCI_VENDOR_ID));
} else {
pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID,
((device & 0xffff) << 16) | (vendor &
0xffff));
}
}
static void gma_read_resources(struct device *dev)
{
pci_dev_read_resources(dev);
@ -703,7 +690,7 @@ gma_write_acpi_tables(struct device *const dev,
}
static struct pci_operations gma_pci_ops = {
.set_subsystem = gma_set_subsystem,
.set_subsystem = pci_dev_set_subsystem,
};
static struct device_operations gma_func0_ops = {

15
src/northbridge/intel/nehalem/northbridge.c
View File

@ -189,19 +189,6 @@ static void mc_set_resources(struct device *dev)
pci_dev_set_resources(dev);
}
static void intel_set_subsystem(struct device *dev, unsigned int vendor,
unsigned int device)
{
if (!vendor || !device) {
pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID,
pci_read_config32(dev, PCI_VENDOR_ID));
} else {
pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID,
((device & 0xffff) << 16) | (vendor &
0xffff));
}
}
static void northbridge_dmi_init(struct device *dev)
{
u32 reg32;
@ -303,7 +290,7 @@ static void northbridge_init(struct device *dev)
}
static struct pci_operations intel_pci_ops = {
.set_subsystem = intel_set_subsystem,
.set_subsystem = pci_dev_set_subsystem,
};
static struct device_operations mc_ops = {

15
src/northbridge/intel/pineview/gma.c
View File

@ -304,19 +304,6 @@ static void gma_func0_init(struct device *dev)
intel_gma_restore_opregion();
}
static void gma_set_subsystem(struct device *dev, unsigned int vendor,
unsigned int device)
{
if (!vendor || !device) {
pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID,
pci_read_config32(dev, PCI_VENDOR_ID));
} else {
pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID,
((device & 0xffff) << 16) | (vendor &
0xffff));
}
}
const struct i915_gpu_controller_info *intel_gma_get_controller_info(void)
{
struct device *dev = pcidev_on_root(0x2, 0);
@ -360,7 +347,7 @@ static const char *gma_acpi_name(const struct device *dev)
}
static struct pci_operations gma_pci_ops = {
.set_subsystem = gma_set_subsystem,
.set_subsystem = pci_dev_set_subsystem,
};
static struct device_operations gma_func0_ops = {

14
src/northbridge/intel/sandybridge/gma.c
View File

@ -653,18 +653,6 @@ static void gma_func0_init(struct device *dev)
intel_gma_restore_opregion();
}
static void gma_set_subsystem(struct device *dev, unsigned int vendor,
unsigned int device)
{
if (!vendor || !device) {
pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID,
pci_read_config32(dev, PCI_VENDOR_ID));
} else {
pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID,
((device & 0xffff) << 16) | (vendor & 0xffff));
}
}
const struct i915_gpu_controller_info *
intel_gma_get_controller_info(void)
{
@ -731,7 +719,7 @@ static void gma_func0_disable(struct device *dev)
}
static struct pci_operations gma_pci_ops = {
.set_subsystem = gma_set_subsystem,
.set_subsystem = pci_dev_set_subsystem,
};
static struct device_operations gma_func0_ops = {

14
src/northbridge/intel/sandybridge/northbridge.c
View File

@ -285,18 +285,6 @@ static void mc_read_resources(struct device *dev)
}
}
static void intel_set_subsystem(struct device *dev, unsigned int vendor,
unsigned int device)
{
if (!vendor || !device) {
pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID,
pci_read_config32(dev, PCI_VENDOR_ID));
} else {
pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID,
((device & 0xffff) << 16) | (vendor & 0xffff));
}
}
static void northbridge_dmi_init(struct device *dev)
{
u32 reg32;
@ -484,7 +472,7 @@ void northbridge_write_smram(u8 smram)
}
static struct pci_operations intel_pci_ops = {
.set_subsystem = intel_set_subsystem,
.set_subsystem = pci_dev_set_subsystem,
};
static struct device_operations mc_ops = {

15
src/northbridge/intel/x4x/gma.c
View File

@ -95,19 +95,6 @@ static void gma_func0_disable(struct device *dev)
pci_write_config16(dev_host, D0F0_GGC, ggc);
}
static void gma_set_subsystem(struct device *dev, unsigned int vendor,
unsigned int device)
{
if (!vendor || !device) {
pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID,
pci_read_config32(dev, PCI_VENDOR_ID));
} else {
pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID,
((device & 0xffff) << 16) | (vendor &
0xffff));
}
}
const struct i915_gpu_controller_info *
intel_gma_get_controller_info(void)
{
@ -159,7 +146,7 @@ static const char *gma_acpi_name(const struct device *dev)
}
static struct pci_operations gma_pci_ops = {
.set_subsystem = gma_set_subsystem,
.set_subsystem = pci_dev_set_subsystem,
};
static struct device_operations gma_func0_ops = {

14
src/soc/intel/baytrail/chip.c
View File

@ -72,18 +72,6 @@ struct chip_operations soc_intel_baytrail_ops = {
.init = soc_init,
};
static void pci_set_subsystem(struct device *dev, unsigned vendor,
unsigned device)
{
if (!vendor || !device) {
pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID,
pci_read_config32(dev, PCI_VENDOR_ID));
} else {
pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID,
((device & 0xffff) << 16) | (vendor & 0xffff));
}
}
struct pci_operations soc_pci_ops = {
.set_subsystem = &pci_set_subsystem,
.set_subsystem = &pci_dev_set_subsystem,
};

16
src/soc/intel/braswell/chip.c
View File

@ -380,22 +380,8 @@ struct chip_operations soc_intel_braswell_ops = {
.init = soc_init,
};
static void pci_set_subsystem(struct device *dev, unsigned int vendor,
unsigned int device)
{
printk(BIOS_SPEW, "%s/%s (%s, 0x%04x, 0x%04x)\n",
__FILE__, __func__, dev_name(dev), vendor, device);
if (!vendor || !device) {
pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID,
pci_read_config32(dev, PCI_VENDOR_ID));
} else {
pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID,
((device & 0xffff) << 16) | (vendor & 0xffff));
}
}
struct pci_operations soc_pci_ops = {
.set_subsystem = &pci_set_subsystem,
.set_subsystem = &pci_dev_set_subsystem,
};
/**

13
src/soc/intel/broadwell/chip.c
View File

@ -64,17 +64,6 @@ struct chip_operations soc_intel_broadwell_ops = {
.init = &broadwell_init_pre_device,
};
static void pci_set_subsystem(struct device *dev, unsigned int vendor,
unsigned int device)
{
if (!vendor || !device)
pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID,
pci_read_config32(dev, PCI_VENDOR_ID));
else
pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID,
(device << 16) | vendor);
}
struct pci_operations broadwell_pci_ops = {
.set_subsystem = &pci_set_subsystem
.set_subsystem = &pci_dev_set_subsystem
};

8
src/soc/intel/broadwell/ehci.c
View File

@ -33,13 +33,7 @@ static void usb_ehci_set_subsystem(struct device *dev, unsigned int vendor,
/* Enable writes to protected registers. */
pci_write_config8(dev, 0x80, access_cntl | 1);
if (!vendor || !device) {
pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID,
pci_read_config32(dev, PCI_VENDOR_ID));
} else {
pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID,
((device & 0xffff) << 16) | (vendor & 0xffff));
}
pci_dev_set_subsystem(dev, vendor, device);
/* Restore protection. */
pci_write_config8(dev, 0x80, access_cntl);

15
src/soc/intel/denverton_ns/chip.c
View File

@ -129,21 +129,8 @@ struct chip_operations soc_intel_denverton_ns_ops = {
.final = soc_final
};
static void soc_set_subsystem(struct device *dev, uint32_t vendor,
uint32_t device)
{
if (!vendor || !device) {
pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID,
pci_read_config32(dev, PCI_VENDOR_ID));
} else {
pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID,
((device & 0xffff) << 16) |
(vendor & 0xffff));
}
}
struct pci_operations soc_pci_ops = {
.set_subsystem = soc_set_subsystem,
.set_subsystem = pci_dev_set_subsystem,
};
/*

13
src/soc/intel/fsp_baytrail/chip.c
View File

@ -74,17 +74,6 @@ struct chip_operations soc_intel_fsp_baytrail_ops = {
.init = soc_init,
};
static void pci_set_subsystem(struct device *dev, unsigned vendor, unsigned device)
{
if (!vendor || !device) {
pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID,
pci_read_config32(dev, PCI_VENDOR_ID));
} else {
pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID,
((device & 0xffff) << 16) | (vendor & 0xffff));
}
}
struct pci_operations soc_pci_ops = {
.set_subsystem = &pci_set_subsystem,
.set_subsystem = &pci_dev_set_subsystem,
};

14
src/soc/intel/fsp_broadwell_de/chip.c
View File

@ -88,18 +88,6 @@ struct chip_operations soc_intel_fsp_broadwell_de_ops = {
.init = soc_init,
};
static void pci_set_subsystem(struct device *dev, unsigned vendor,
unsigned device)
{
if (!vendor || !device) {
pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID,
pci_read_config32(dev, PCI_VENDOR_ID));
} else {
pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID,
((device & 0xffff) << 16) | (vendor & 0xffff));
}
}
struct pci_operations soc_pci_ops = {
.set_subsystem = &pci_set_subsystem,
.set_subsystem = &pci_dev_set_subsystem,
};

14
src/southbridge/intel/bd82x6x/azalia.c
View File

@ -336,20 +336,8 @@ static const char *azalia_acpi_name(const struct device *dev)
return "HDEF";
}
static void azalia_set_subsystem(struct device *dev, unsigned vendor,
unsigned device)
{
if (!vendor || !device) {
pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID,
pci_read_config32(dev, PCI_VENDOR_ID));
} else {
pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID,
((device & 0xffff) << 16) | (vendor & 0xffff));
}
}
static struct pci_operations azalia_pci_ops = {
.set_subsystem = azalia_set_subsystem,
.set_subsystem = pci_dev_set_subsystem,
};
static struct device_operations azalia_ops = {

13
src/southbridge/intel/bd82x6x/lpc.c
View File

@ -694,17 +694,6 @@ static void pch_lpc_enable(struct device *dev)
pch_enable(dev);
}
static void set_subsystem(struct device *dev, unsigned vendor, unsigned device)
{
if (!vendor || !device) {
pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID,
pci_read_config32(dev, PCI_VENDOR_ID));
} else {
pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID,
((device & 0xffff) << 16) | (vendor & 0xffff));
}
}
static void southbridge_inject_dsdt(struct device *dev)
{
global_nvs_t *gnvs = cbmem_add (CBMEM_ID_ACPI_GNVS, sizeof(*gnvs));
@ -924,7 +913,7 @@ static void lpc_final(struct device *dev)
}
static struct pci_operations pci_ops = {
.set_subsystem = set_subsystem,
.set_subsystem = pci_dev_set_subsystem,
};
static struct device_operations device_ops = {

13
src/southbridge/intel/bd82x6x/me.c
View File

@ -735,19 +735,8 @@ static void intel_me_init(struct device *dev)
}
}
static void set_subsystem(struct device *dev, unsigned vendor, unsigned device)
{
if (!vendor || !device) {
pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID,
pci_read_config32(dev, PCI_VENDOR_ID));
} else {
pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID,
((device & 0xffff) << 16) | (vendor & 0xffff));
}
}
static struct pci_operations pci_ops = {
.set_subsystem = set_subsystem,
.set_subsystem = pci_dev_set_subsystem,
};
static struct device_operations device_ops = {

13
src/southbridge/intel/bd82x6x/me_8.x.c
View File

@ -738,19 +738,8 @@ static void intel_me_init(struct device *dev)
}
}
static void set_subsystem(struct device *dev, unsigned vendor, unsigned device)
{
if (!vendor || !device) {
pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID,
pci_read_config32(dev, PCI_VENDOR_ID));
} else {
pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID,
((device & 0xffff) << 16) | (vendor & 0xffff));
}
}
static struct pci_operations pci_ops = {
.set_subsystem = set_subsystem,
.set_subsystem = pci_dev_set_subsystem,
};
static struct device_operations device_ops = {

14
src/southbridge/intel/bd82x6x/sata.c
View File

@ -234,18 +234,6 @@ static void sata_enable(struct device *dev)
pci_write_config16(dev, 0x90, map);
}
static void sata_set_subsystem(struct device *dev, unsigned vendor,
unsigned device)
{
if (!vendor || !device) {
pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID,
pci_read_config32(dev, PCI_VENDOR_ID));
} else {
pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID,
((device & 0xffff) << 16) | (vendor & 0xffff));
}
}
static const char *sata_acpi_name(const struct device *dev)
{
return "SATA";
@ -258,7 +246,7 @@ static void sata_fill_ssdt(struct device *dev)
}
static struct pci_operations sata_pci_ops = {
.set_subsystem = sata_set_subsystem,
.set_subsystem = pci_dev_set_subsystem,
};
static struct device_operations sata_ops = {

14
src/southbridge/intel/bd82x6x/smbus.c
View File

@ -71,20 +71,8 @@ static struct smbus_bus_operations lops_smbus_bus = {
.write_byte = lsmbus_write_byte,
};
static void smbus_set_subsystem(struct device *dev, unsigned vendor,
unsigned device)
{
if (!vendor || !device) {
pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID,
pci_read_config32(dev, PCI_VENDOR_ID));
} else {
pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID,
((device & 0xffff) << 16) | (vendor & 0xffff));
}
}
static struct pci_operations smbus_pci_ops = {
.set_subsystem = smbus_set_subsystem,
.set_subsystem = pci_dev_set_subsystem,
};
static void smbus_read_resources(struct device *dev)

8
src/southbridge/intel/bd82x6x/usb_ehci.c
View File

@ -84,13 +84,7 @@ static void usb_ehci_set_subsystem(struct device *dev, unsigned vendor,
/* Enable writes to protected registers. */
pci_write_config8(dev, 0x80, access_cntl | 1);
if (!vendor || !device) {
pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID,
pci_read_config32(dev, PCI_VENDOR_ID));
} else {
pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID,
((device & 0xffff) << 16) | (vendor & 0xffff));
}
pci_dev_set_subsystem(dev, vendor, device);
/* Restore protection. */
pci_write_config8(dev, 0x80, access_cntl);

14
src/southbridge/intel/bd82x6x/usb_xhci.c
View File

@ -56,20 +56,8 @@ static const char *xhci_acpi_name(const struct device *dev)
return "XHC";
}
static void xhci_set_subsystem(struct device *dev, unsigned vendor,
unsigned device)
{
if (!vendor || !device) {
pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID,
pci_read_config32(dev, PCI_VENDOR_ID));
} else {
pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID,
((device & 0xffff) << 16) | (vendor & 0xffff));
}
}
static struct pci_operations xhci_pci_ops = {
.set_subsystem = xhci_set_subsystem,
.set_subsystem = pci_dev_set_subsystem,
};
static struct device_operations usb_xhci_ops = {

13
src/southbridge/intel/fsp_rangeley/lpc.c
View File

@ -417,17 +417,6 @@ static void soc_lpc_enable(struct device *dev)
soc_enable(dev);
}
static void set_subsystem(struct device *dev, unsigned vendor, unsigned device)
{
if (!vendor || !device) {
pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID,
pci_read_config32(dev, PCI_VENDOR_ID));
} else {
pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID,
((device & 0xffff) << 16) | (vendor & 0xffff));
}
}
static void southbridge_inject_dsdt(struct device *dev)
{
global_nvs_t *gnvs = cbmem_add (CBMEM_ID_ACPI_GNVS, sizeof(*gnvs));
@ -448,7 +437,7 @@ static void southbridge_inject_dsdt(struct device *dev)
}
static struct pci_operations pci_ops = {
.set_subsystem = set_subsystem,
.set_subsystem = pci_dev_set_subsystem,
};
static struct device_operations device_ops = {

13
src/southbridge/intel/fsp_rangeley/sata.c
View File

@ -96,19 +96,8 @@ static void sata_enable(struct device *dev)
{
}
static void sata_set_subsystem(struct device *dev, unsigned vendor, unsigned device)
{
if (!vendor || !device) {
pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID,
pci_read_config32(dev, PCI_VENDOR_ID));
} else {
pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID,
((device & 0xffff) << 16) | (vendor & 0xffff));
}
}
static struct pci_operations sata_pci_ops = {
.set_subsystem = sata_set_subsystem,
.set_subsystem = pci_dev_set_subsystem,
};
static struct device_operations sata_ops = {

14
src/southbridge/intel/fsp_rangeley/smbus.c
View File

@ -40,20 +40,8 @@ static struct smbus_bus_operations lops_smbus_bus = {
.read_byte = lsmbus_read_byte,
};
static void smbus_set_subsystem(struct device *dev, unsigned vendor,
unsigned device)
{
if (!vendor || !device) {
pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID,
pci_read_config32(dev, PCI_VENDOR_ID));
} else {
pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID,
((device & 0xffff) << 16) | (vendor & 0xffff));
}
}
static struct pci_operations smbus_pci_ops = {
.set_subsystem = smbus_set_subsystem,
.set_subsystem = pci_dev_set_subsystem,
};
static void rangeley_smbus_read_resources(struct device *dev)

14
src/southbridge/intel/i82801gx/ac97.c
View File

@ -247,20 +247,8 @@ static void ac97_modem_init(struct device *dev)
}
}
static void ac97_set_subsystem(struct device *dev, unsigned int vendor,
unsigned int device)
{
if (!vendor || !device) {
pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID,
pci_read_config32(dev, PCI_VENDOR_ID));
} else {
pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID,
((device & 0xffff) << 16) | (vendor & 0xffff));
}
}
static struct pci_operations ac97_pci_ops = {
.set_subsystem = ac97_set_subsystem,
.set_subsystem = pci_dev_set_subsystem,
};
static struct device_operations ac97_audio_ops = {

14
src/southbridge/intel/i82801gx/azalia.c
View File

@ -303,20 +303,8 @@ static void azalia_init(struct device *dev)
}
}
static void azalia_set_subsystem(struct device *dev, unsigned int vendor,
unsigned int device)
{
if (!vendor || !device) {
pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID,
pci_read_config32(dev, PCI_VENDOR_ID));
} else {
pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID,
((device & 0xffff) << 16) | (vendor & 0xffff));
}
}
static struct pci_operations azalia_pci_ops = {
.set_subsystem = azalia_set_subsystem,
.set_subsystem = pci_dev_set_subsystem,
};
static struct device_operations azalia_ops = {

14
src/southbridge/intel/i82801gx/ide.c
View File

@ -92,20 +92,8 @@ static void ide_init(struct device *dev)
printk(BIOS_DEBUG, "\n");
}
static void ide_set_subsystem(struct device *dev, unsigned int vendor,
unsigned int device)
{
if (!vendor || !device) {
pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID,
pci_read_config32(dev, PCI_VENDOR_ID));
} else {
pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID,
((device & 0xffff) << 16) | (vendor & 0xffff));
}
}
static struct pci_operations ide_pci_ops = {
.set_subsystem = ide_set_subsystem,
.set_subsystem = pci_dev_set_subsystem,
};
static struct device_operations ide_ops = {

14
src/southbridge/intel/i82801gx/lpc.c
View File

@ -676,18 +676,6 @@ static void lpc_final(struct device *dev)
outb(POST_OS_BOOT, 0x80);
}
static void set_subsystem(struct device *dev, unsigned int vendor,
unsigned int device)
{
if (!vendor || !device) {
pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID,
pci_read_config32(dev, PCI_VENDOR_ID));
} else {
pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID,
((device & 0xffff) << 16) | (vendor & 0xffff));
}
}
static void southbridge_inject_dsdt(struct device *dev)
{
global_nvs_t *gnvs = cbmem_add(CBMEM_ID_ACPI_GNVS, sizeof(*gnvs));
@ -728,7 +716,7 @@ static void southbridge_fill_ssdt(struct device *device)
}
static struct pci_operations pci_ops = {
.set_subsystem = set_subsystem,
.set_subsystem = pci_dev_set_subsystem,
};
static struct device_operations device_ops = {

14
src/southbridge/intel/i82801gx/sata.c
View File

@ -200,20 +200,8 @@ static void sata_init(struct device *dev)
pci_write_config32(dev, SATA_IR, reg32);
}
static void sata_set_subsystem(struct device *dev, unsigned int vendor,
unsigned int device)
{
if (!vendor || !device) {
pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID,
pci_read_config32(dev, PCI_VENDOR_ID));
} else {
pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID,
((device & 0xffff) << 16) | (vendor & 0xffff));
}
}
static struct pci_operations sata_pci_ops = {
.set_subsystem = sata_set_subsystem,
.set_subsystem = pci_dev_set_subsystem,
};
static struct device_operations sata_ops = {

14
src/southbridge/intel/i82801gx/smbus.c
View File

@ -81,20 +81,8 @@ static struct smbus_bus_operations lops_smbus_bus = {
.block_write = lsmbus_block_write,
};
static void smbus_set_subsystem(struct device *dev, unsigned int vendor,
unsigned int device)
{
if (!vendor || !device) {
pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID,
pci_read_config32(dev, PCI_VENDOR_ID));
} else {
pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID,
((device & 0xffff) << 16) | (vendor & 0xffff));
}
}
static struct pci_operations smbus_pci_ops = {
.set_subsystem = smbus_set_subsystem,
.set_subsystem = pci_dev_set_subsystem,
};
static void smbus_read_resources(struct device *dev)

14
src/southbridge/intel/i82801gx/usb.c
View File

@ -43,20 +43,8 @@ static void usb_init(struct device *dev)
printk(BIOS_DEBUG, "done.\n");
}
static void usb_set_subsystem(struct device *dev, unsigned int vendor,
unsigned int device)
{
if (!vendor || !device) {
pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID,
pci_read_config32(dev, PCI_VENDOR_ID));
} else {
pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID,
((device & 0xffff) << 16) | (vendor & 0xffff));
}
}
static struct pci_operations usb_pci_ops = {
.set_subsystem = usb_set_subsystem,
.set_subsystem = pci_dev_set_subsystem,
};
static struct device_operations usb_ops = {

8
src/southbridge/intel/i82801gx/usb_ehci.c
View File

@ -69,13 +69,7 @@ static void usb_ehci_set_subsystem(struct device *dev, unsigned int vendor,
/* Enable writes to protected registers. */
pci_write_config8(dev, 0x80, access_cntl | 1);
if (!vendor || !device) {
pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID,
pci_read_config32(dev, PCI_VENDOR_ID));
} else {
pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID,
((device & 0xffff) << 16) | (vendor & 0xffff));
}
pci_dev_set_subsystem(dev, vendor, device);
/* Restore protection. */
pci_write_config8(dev, 0x80, access_cntl);

14
src/southbridge/intel/i82801ix/hdaudio.c
View File

@ -287,20 +287,8 @@ static void azalia_init(struct device *dev)
}
}
static void azalia_set_subsystem(struct device *dev, unsigned vendor,
unsigned device)
{
if (!vendor || !device) {
pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID,
pci_read_config32(dev, PCI_VENDOR_ID));
} else {
pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID,
((device & 0xffff) << 16) | (vendor & 0xffff));
}
}
static struct pci_operations azalia_pci_ops = {
.set_subsystem = azalia_set_subsystem,
.set_subsystem = pci_dev_set_subsystem,
};
static struct device_operations azalia_ops = {

13
src/southbridge/intel/i82801ix/lpc.c
View File

@ -527,17 +527,6 @@ static void i82801ix_lpc_read_resources(struct device *dev)
res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
}
static void set_subsystem(struct device *dev, unsigned vendor, unsigned device)
{
if (!vendor || !device) {
pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID,
pci_read_config32(dev, PCI_VENDOR_ID));
} else {
pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID,
((device & 0xffff) << 16) | (vendor & 0xffff));
}
}
static void southbridge_inject_dsdt(struct device *dev)
{
global_nvs_t *gnvs = cbmem_add (CBMEM_ID_ACPI_GNVS, sizeof(*gnvs));
@ -578,7 +567,7 @@ static void southbridge_fill_ssdt(struct device *device)
}
static struct pci_operations pci_ops = {
.set_subsystem = set_subsystem,
.set_subsystem = pci_dev_set_subsystem,
};
static struct device_operations device_ops = {

14
src/southbridge/intel/i82801ix/sata.c
View File

@ -258,20 +258,8 @@ static void sata_enable(struct device *dev)
pci_write_config16(dev, 0x90, map);
}
static void sata_set_subsystem(struct device *dev, unsigned vendor,
unsigned device)
{
if (!vendor || !device) {
pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID,
pci_read_config32(dev, PCI_VENDOR_ID));
} else {
pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID,
((device & 0xffff) << 16) | (vendor & 0xffff));
}
}
static struct pci_operations sata_pci_ops = {
.set_subsystem = sata_set_subsystem,
.set_subsystem = pci_dev_set_subsystem,
};
static struct device_operations sata_ops = {

14
src/southbridge/intel/i82801ix/smbus.c
View File

@ -64,20 +64,8 @@ static struct smbus_bus_operations lops_smbus_bus = {
.write_byte = lsmbus_write_byte,
};
static void smbus_set_subsystem(struct device *dev, unsigned vendor,
unsigned device)
{
if (!vendor || !device) {
pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID,
pci_read_config32(dev, PCI_VENDOR_ID));
} else {
pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID,
((device & 0xffff) << 16) | (vendor & 0xffff));
}
}
static struct pci_operations smbus_pci_ops = {
.set_subsystem = smbus_set_subsystem,
.set_subsystem = pci_dev_set_subsystem,
};
static void smbus_read_resources(struct device *dev)

14
src/southbridge/intel/i82801ix/thermal.c
View File

@ -51,20 +51,8 @@ static void thermal_init(struct device *dev)
pci_write_config32(dev, 0x10, 0);
}
static void thermal_set_subsystem(struct device *dev, unsigned vendor,
unsigned device)
{
if (!vendor || !device) {
pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID,
pci_read_config32(dev, PCI_VENDOR_ID));
} else {
pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID,
((device & 0xffff) << 16) | (vendor & 0xffff));
}
}
static struct pci_operations thermal_pci_ops = {
.set_subsystem = thermal_set_subsystem,
.set_subsystem = pci_dev_set_subsystem,
};
static struct device_operations device_ops = {

8
src/southbridge/intel/i82801ix/usb_ehci.c
View File

@ -44,13 +44,7 @@ static void usb_ehci_set_subsystem(struct device *dev, unsigned vendor,
/* Enable writes to protected registers. */
pci_write_config8(dev, 0x80, access_cntl | 1);
if (!vendor || !device) {
pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID,
pci_read_config32(dev, PCI_VENDOR_ID));
} else {
pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID,
((device & 0xffff) << 16) | (vendor & 0xffff));
}
pci_dev_set_subsystem(dev, vendor, device);
/* Restore protection. */
pci_write_config8(dev, 0x80, access_cntl);

14
src/southbridge/intel/i82801jx/hdaudio.c
View File

@ -287,20 +287,8 @@ static void azalia_init(struct device *dev)
}
}
static void azalia_set_subsystem(struct device *dev, unsigned vendor,
unsigned device)
{
if (!vendor || !device) {
pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID,
pci_read_config32(dev, PCI_VENDOR_ID));
} else {
pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID,
((device & 0xffff) << 16) | (vendor & 0xffff));
}
}
static struct pci_operations azalia_pci_ops = {
.set_subsystem = azalia_set_subsystem,
.set_subsystem = pci_dev_set_subsystem,
};
static struct device_operations azalia_ops = {

13
src/southbridge/intel/i82801jx/lpc.c
View File

@ -684,17 +684,6 @@ static void i82801jx_lpc_read_resources(struct device *dev)
}
}
static void set_subsystem(struct device *dev, unsigned vendor, unsigned device)
{
if (!vendor || !device) {
pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID,
pci_read_config32(dev, PCI_VENDOR_ID));
} else {
pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID,
((device & 0xffff) << 16) | (vendor & 0xffff));
}
}
static void southbridge_inject_dsdt(struct device *dev)
{
global_nvs_t *gnvs = cbmem_add (CBMEM_ID_ACPI_GNVS, sizeof(*gnvs));
@ -734,7 +723,7 @@ static void southbridge_fill_ssdt(struct device *device)
}
static struct pci_operations pci_ops = {
.set_subsystem = set_subsystem,
.set_subsystem = pci_dev_set_subsystem,
};
static struct device_operations device_ops = {

14
src/southbridge/intel/i82801jx/sata.c
View File

@ -253,20 +253,8 @@ static void sata_enable(struct device *dev)
pci_write_config16(dev, 0x90, map);
}
static void sata_set_subsystem(struct device *dev, unsigned vendor,
unsigned device)
{
if (!vendor || !device) {
pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID,
pci_read_config32(dev, PCI_VENDOR_ID));
} else {
pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID,
((device & 0xffff) << 16) | (vendor & 0xffff));
}
}
static struct pci_operations sata_pci_ops = {
.set_subsystem = sata_set_subsystem,
.set_subsystem = pci_dev_set_subsystem,
};
static struct device_operations sata_ops = {

14
src/southbridge/intel/i82801jx/smbus.c
View File

@ -91,20 +91,8 @@ static struct smbus_bus_operations lops_smbus_bus = {
.block_write = lsmbus_block_write,
};
static void smbus_set_subsystem(struct device *dev, unsigned vendor,
unsigned device)
{
if (!vendor || !device) {
pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID,
pci_read_config32(dev, PCI_VENDOR_ID));
} else {
pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID,
((device & 0xffff) << 16) | (vendor & 0xffff));
}
}
static struct pci_operations smbus_pci_ops = {
.set_subsystem = smbus_set_subsystem,
.set_subsystem = pci_dev_set_subsystem,
};
static void smbus_read_resources(struct device *dev)

14
src/southbridge/intel/i82801jx/thermal.c
View File

@ -51,20 +51,8 @@ static void thermal_init(struct device *dev)
pci_write_config32(dev, 0x10, 0);
}
static void thermal_set_subsystem(struct device *dev, unsigned vendor,
unsigned device)
{
if (!vendor || !device) {
pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID,
pci_read_config32(dev, PCI_VENDOR_ID));
} else {
pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID,
((device & 0xffff) << 16) | (vendor & 0xffff));
}
}
static struct pci_operations thermal_pci_ops = {
.set_subsystem = thermal_set_subsystem,
.set_subsystem = pci_dev_set_subsystem,
};
static struct device_operations device_ops = {

8
src/southbridge/intel/i82801jx/usb_ehci.c
View File

@ -44,13 +44,7 @@ static void usb_ehci_set_subsystem(struct device *dev, unsigned vendor,
/* Enable writes to protected registers. */
pci_write_config8(dev, 0x80, access_cntl | 1);
if (!vendor || !device) {
pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID,
pci_read_config32(dev, PCI_VENDOR_ID));
} else {
pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID,
((device & 0xffff) << 16) | (vendor & 0xffff));
}
pci_dev_set_subsystem(dev, vendor, device);
/* Restore protection. */
pci_write_config8(dev, 0x80, access_cntl);

14
src/southbridge/intel/ibexpeak/azalia.c
View File

@ -313,20 +313,8 @@ static void azalia_init(struct device *dev)
pci_write_config8(dev, 0x43, reg8);
}
static void azalia_set_subsystem(struct device *dev, unsigned vendor,
unsigned device)
{
if (!vendor || !device) {
pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID,
pci_read_config32(dev, PCI_VENDOR_ID));
} else {
pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID,
((device & 0xffff) << 16) | (vendor & 0xffff));
}
}
static struct pci_operations azalia_pci_ops = {
.set_subsystem = azalia_set_subsystem,
.set_subsystem = pci_dev_set_subsystem,
};
static struct device_operations azalia_ops = {

14
src/southbridge/intel/ibexpeak/lpc.c
View File

@ -609,18 +609,6 @@ static void pch_lpc_enable(struct device *dev)
pch_enable(dev);
}
static void set_subsystem(struct device *dev, unsigned vendor,
unsigned device)
{
if (!vendor || !device) {
pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID,
pci_read_config32(dev, PCI_VENDOR_ID));
} else {
pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID,
((device & 0xffff) << 16) | (vendor & 0xffff));
}
}
static void southbridge_inject_dsdt(struct device *dev)
{
global_nvs_t *gnvs = cbmem_add (CBMEM_ID_ACPI_GNVS, sizeof(*gnvs));
@ -807,7 +795,7 @@ static void lpc_final(struct device *dev)
}
static struct pci_operations pci_ops = {
.set_subsystem = set_subsystem,
.set_subsystem = pci_dev_set_subsystem,
};
static struct device_operations device_ops = {

14
src/southbridge/intel/ibexpeak/me.c
View File

@ -610,20 +610,8 @@ static void intel_me_init(struct device *dev)
}
}
static void set_subsystem(struct device *dev, unsigned vendor,
unsigned device)
{
if (!vendor || !device) {
pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID,
pci_read_config32(dev, PCI_VENDOR_ID));
} else {
pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID,
((device & 0xffff) << 16) | (vendor & 0xffff));
}
}
static struct pci_operations pci_ops = {
.set_subsystem = set_subsystem,
.set_subsystem = pci_dev_set_subsystem,
};
static struct device_operations device_ops = {

15
src/southbridge/intel/ibexpeak/sata.c
View File

@ -235,19 +235,6 @@ static void sata_enable(struct device *dev)
pci_write_config16(dev, 0x90, map);
}
static void sata_set_subsystem(struct device *dev, unsigned vendor,
unsigned device)
{
if (!vendor || !device) {
pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID,
pci_read_config32(dev, PCI_VENDOR_ID));
} else {
pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID,
((device & 0xffff) << 16) | (vendor &
0xffff));
}
}
static void sata_fill_ssdt(struct device *dev)
{
config_t *config = dev->chip_info;
@ -255,7 +242,7 @@ static void sata_fill_ssdt(struct device *dev)
}
static struct pci_operations sata_pci_ops = {
.set_subsystem = sata_set_subsystem,
.set_subsystem = pci_dev_set_subsystem,
};
static struct device_operations sata_ops = {

14
src/southbridge/intel/ibexpeak/smbus.c
View File

@ -71,20 +71,8 @@ static struct smbus_bus_operations lops_smbus_bus = {
.write_byte = lsmbus_write_byte,
};
static void smbus_set_subsystem(struct device *dev, unsigned vendor,
unsigned device)
{
if (!vendor || !device) {
pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID,
pci_read_config32(dev, PCI_VENDOR_ID));
} else {
pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID,
((device & 0xffff) << 16) | (vendor & 0xffff));
}
}
static struct pci_operations smbus_pci_ops = {
.set_subsystem = smbus_set_subsystem,
.set_subsystem = pci_dev_set_subsystem,
};
static void smbus_read_resources(struct device *dev)

15
src/southbridge/intel/ibexpeak/thermal.c
View File

@ -45,21 +45,8 @@ static void thermal_init(struct device *dev)
printk(BIOS_DEBUG, "Thermal init done.\n");
}
static void set_subsystem(struct device *dev, unsigned vendor,
unsigned device)
{
if (!vendor || !device) {
pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID,
pci_read_config32(dev, PCI_VENDOR_ID));
} else {
pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID,
((device & 0xffff) << 16) | (vendor &
0xffff));
}
}
static struct pci_operations pci_ops = {
.set_subsystem = set_subsystem,
.set_subsystem = pci_dev_set_subsystem,
};
static struct device_operations thermal_ops = {

9
src/southbridge/intel/ibexpeak/usb_ehci.c
View File

@ -78,14 +78,7 @@ static void usb_ehci_set_subsystem(struct device *dev, unsigned vendor,
/* Enable writes to protected registers. */
pci_write_config8(dev, 0x80, access_cntl | 1);
if (!vendor || !device) {
pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID,
pci_read_config32(dev, PCI_VENDOR_ID));
} else {
pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID,
((device & 0xffff) << 16) | (vendor &
0xffff));
}
pci_dev_set_subsystem(dev, vendor, device);
/* Restore protection. */
pci_write_config8(dev, 0x80, access_cntl);

14
src/southbridge/intel/lynxpoint/azalia.c
View File

@ -154,20 +154,8 @@ static void azalia_init(struct device *dev)
}
}
static void azalia_set_subsystem(struct device *dev, unsigned int vendor,
unsigned int device)
{
if (!vendor || !device) {
pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID,
pci_read_config32(dev, PCI_VENDOR_ID));
} else {
pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID,
((device & 0xffff) << 16) | (vendor & 0xffff));
}
}
static struct pci_operations azalia_pci_ops = {
.set_subsystem = azalia_set_subsystem,
.set_subsystem = pci_dev_set_subsystem,
};
static struct device_operations azalia_ops = {

13
src/southbridge/intel/lynxpoint/lpc.c
View File

@ -723,17 +723,6 @@ static void pch_lpc_enable(struct device *dev)
pch_enable(dev);
}
static void set_subsystem(struct device *dev, unsigned vendor, unsigned device)
{
if (!vendor || !device) {
pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID,
pci_read_config32(dev, PCI_VENDOR_ID));
} else {
pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID,
((device & 0xffff) << 16) | (vendor & 0xffff));
}
}
static void southbridge_inject_dsdt(struct device *dev)
{
global_nvs_t *gnvs;
@ -981,7 +970,7 @@ static void lpc_final(struct device *dev)
}
static struct pci_operations pci_ops = {
.set_subsystem = set_subsystem,
.set_subsystem = pci_dev_set_subsystem,
};
static struct device_operations device_ops = {

14
src/southbridge/intel/lynxpoint/me_9.x.c
View File

@ -874,20 +874,8 @@ static void intel_me_init(struct device *dev)
*/
}
static void set_subsystem(struct device *dev, unsigned int vendor,
unsigned int device)
{
if (!vendor || !device) {
pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID,
pci_read_config32(dev, PCI_VENDOR_ID));
} else {
pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID,
((device & 0xffff) << 16) | (vendor & 0xffff));
}
}
static struct pci_operations pci_ops = {
.set_subsystem = set_subsystem,
.set_subsystem = pci_dev_set_subsystem,
};
static void intel_me_enable(struct device *dev)

14
src/southbridge/intel/lynxpoint/sata.c
View File

@ -323,20 +323,8 @@ static void sata_enable(struct device *dev)
pci_write_config16(dev, 0x90, map);
}
static void sata_set_subsystem(struct device *dev, unsigned vendor,
unsigned device)
{
if (!vendor || !device) {
pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID,
pci_read_config32(dev, PCI_VENDOR_ID));
} else {
pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID,
((device & 0xffff) << 16) | (vendor & 0xffff));
}
}
static struct pci_operations sata_pci_ops = {
.set_subsystem = sata_set_subsystem,
.set_subsystem = pci_dev_set_subsystem,
};
static struct device_operations sata_ops = {

14
src/southbridge/intel/lynxpoint/serialio.c
View File

@ -237,20 +237,8 @@ static void serialio_init(struct device *dev)
}
}
static void serialio_set_subsystem(struct device *dev, unsigned int vendor,
unsigned int device)
{
if (!vendor || !device) {
pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID,
pci_read_config32(dev, PCI_VENDOR_ID));
} else {
pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID,
((device & 0xffff) << 16) | (vendor & 0xffff));
}
}
static struct pci_operations pci_ops = {
.set_subsystem = serialio_set_subsystem,
.set_subsystem = pci_dev_set_subsystem,
};
static struct device_operations device_ops = {

14
src/southbridge/intel/lynxpoint/smbus.c
View File

@ -70,20 +70,8 @@ static struct smbus_bus_operations lops_smbus_bus = {
.write_byte = lsmbus_write_byte,
};
static void smbus_set_subsystem(struct device *dev, unsigned int vendor,
unsigned int device)
{
if (!vendor || !device) {
pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID,
pci_read_config32(dev, PCI_VENDOR_ID));
} else {
pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID,
((device & 0xffff) << 16) | (vendor & 0xffff));
}
}
static struct pci_operations smbus_pci_ops = {
.set_subsystem = smbus_set_subsystem,
.set_subsystem = pci_dev_set_subsystem,
};
static void smbus_read_resources(struct device *dev)

8
src/southbridge/intel/lynxpoint/usb_ehci.c
View File

@ -175,13 +175,7 @@ static void usb_ehci_set_subsystem(struct device *dev, unsigned int vendor,
/* Enable writes to protected registers. */
pci_write_config8(dev, 0x80, access_cntl | 1);
if (!vendor || !device) {
pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID,
pci_read_config32(dev, PCI_VENDOR_ID));
} else {
pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID,
((device & 0xffff) << 16) | (vendor & 0xffff));
}
pci_dev_set_subsystem(dev, vendor, device);
/* Restore protection. */
pci_write_config8(dev, 0x80, access_cntl);

14
src/southbridge/intel/lynxpoint/usb_xhci.c
View File

@ -373,20 +373,8 @@ static void usb_xhci_init(struct device *dev)
}
}
static void usb_xhci_set_subsystem(struct device *dev, unsigned int vendor,
unsigned int device)
{
if (!vendor || !device) {
pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID,
pci_read_config32(dev, PCI_VENDOR_ID));
} else {
pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID,
((device & 0xffff) << 16) | (vendor & 0xffff));
}
}
static struct pci_operations lops_pci = {
.set_subsystem = &usb_xhci_set_subsystem,
.set_subsystem = &pci_dev_set_subsystem,
};
static struct device_operations usb_xhci_ops = {

14
src/southbridge/nvidia/mcp55/azalia.c
View File

@ -254,20 +254,8 @@ static void azalia_init(struct device *dev)
#endif
}
static void azalia_set_subsystem(struct device *dev, unsigned vendor,
unsigned device)
{
if (!vendor || !device) {
pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID,
pci_read_config32(dev, PCI_VENDOR_ID));
} else {
pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID,
((device & 0xffff) << 16) | (vendor & 0xffff));
}
}
static struct pci_operations azalia_pci_ops = {
.set_subsystem = azalia_set_subsystem,
.set_subsystem = pci_dev_set_subsystem,
};
static struct device_operations azalia_ops = {