soc/intel/common/block: Don't use device_t in ramstage
Use of device_t has been abandoned in ramstage. Change-Id: If2d643eafea854563f56a7f867b7b492b6d09a19 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/28631 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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@ -42,7 +42,7 @@ void soc_write_sci_irq_select(uint32_t scis);
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* Calls acpi_write_hpet which creates and fills HPET table and
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* adds it to the RSDT (and XSDT) structure.
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*/
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unsigned long southbridge_write_acpi_tables(device_t device,
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unsigned long southbridge_write_acpi_tables(struct device *device,
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unsigned long current,
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struct acpi_rsdp *rsdp);
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@ -50,7 +50,7 @@ unsigned long southbridge_write_acpi_tables(device_t device,
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* Creates acpi gnvs and adds it to the DSDT table.
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* GNVS creation is chipset specific and is done in soc specific acpi.c file.
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*/
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void southbridge_inject_dsdt(device_t device);
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void southbridge_inject_dsdt(struct device *device);
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/*
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* This function populates the gnvs structure in acpi table.
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@ -34,7 +34,7 @@ void graphics_soc_init(struct device *dev);
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/*
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* Write ASL entry for Graphics opregion
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* Input:
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* device_t device: device structure
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* struct device *device: device structure
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* current: start address of graphics opregion
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* rsdp: pointer to RSDT (and XSDT) structure
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*
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@ -75,7 +75,7 @@ void get_microcode_info(const void **microcode, int *parallel);
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* In this function SOC must perform CPU feature programming
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* during Ramstage phase.
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*/
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void soc_core_init(device_t dev);
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void soc_core_init(struct device *dev);
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/*
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* In this function SOC must fill required mp_ops params, also it
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@ -46,7 +46,7 @@ void pch_lpc_add_new_resource(struct device *dev, uint8_t offset,
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res->flags = flags;
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}
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static void pch_lpc_add_io_resources(device_t dev)
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static void pch_lpc_add_io_resources(struct device *dev)
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{
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/* Add the default claimed legacy IO range for the LPC device. */
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pch_lpc_add_new_resource(dev, 0, 0, 0x1000, IORESOURCE_IO |
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@ -56,7 +56,7 @@ static void pch_lpc_add_io_resources(device_t dev)
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pch_lpc_soc_fill_io_resources(dev);
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}
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static void pch_lpc_read_resources(device_t dev)
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static void pch_lpc_read_resources(struct device *dev)
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{
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/* Get the PCI resources of this device. */
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pci_dev_read_resources(dev);
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@ -101,7 +101,7 @@ static void pch_lpc_set_child_resources(struct device *dev)
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}
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}
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static void pch_lpc_set_resources(device_t dev)
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static void pch_lpc_set_resources(struct device *dev)
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{
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pci_dev_set_resources(dev);
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@ -64,7 +64,7 @@ static void pch_pcie_init(struct device *dev)
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pci_write_config16(dev, PCI_SEC_STATUS, reg16);
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}
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static void pcie_set_L1_ss_max_latency(device_t dev, unsigned int offset)
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static void pcie_set_L1_ss_max_latency(struct device *dev, unsigned int offset)
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{
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/* Set max snoop and non-snoop latency for the SOC */
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pci_write_config32(dev, offset,
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@ -22,7 +22,7 @@
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#include <soc/smbus.h>
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#include "smbuslib.h"
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static int lsmbus_read_byte(device_t dev, u8 address)
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static int lsmbus_read_byte(struct device *dev, u8 address)
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{
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u16 device;
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struct resource *res;
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@ -33,7 +33,7 @@ static int lsmbus_read_byte(device_t dev, u8 address)
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return smbus_read8(res->base, device, address);
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}
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static int lsmbus_write_byte(device_t dev, u8 address, u8 data)
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static int lsmbus_write_byte(struct device *dev, u8 address, u8 data)
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{
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u16 device;
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struct resource *res;
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@ -50,7 +50,7 @@ static struct smbus_bus_operations lops_smbus_bus = {
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.write_byte = lsmbus_write_byte,
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};
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static void pch_smbus_init(device_t dev)
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static void pch_smbus_init(struct device *dev)
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{
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struct resource *res;
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@ -64,7 +64,7 @@ static void pch_smbus_init(device_t dev)
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outb(SMBUS_SLAVE_ADDR, res->base + SMB_RCV_SLVA);
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}
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static void smbus_read_resources(device_t dev)
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static void smbus_read_resources(struct device *dev)
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{
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struct resource *res = new_resource(dev, PCI_BASE_ADDRESS_4);
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res->base = SMBUS_IO_BASE;
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@ -88,7 +88,7 @@ static const struct sa_mem_map_descriptor sa_memory_map[MAX_MAP_ENTRIES] = {
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};
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/* Read DRAM memory map register value through PCI configuration space */
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static void sa_read_map_entry(device_t dev,
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static void sa_read_map_entry(struct device *dev,
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const struct sa_mem_map_descriptor *entry, uint64_t *result)
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{
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uint64_t value = 0;
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@ -213,7 +213,8 @@ static bool is_imr_enabled(uint32_t imr_base_reg)
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return !!(imr_base_reg & (1 << 31));
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}
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static void imr_resource(device_t dev, int idx, uint32_t base, uint32_t mask)
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static void imr_resource(struct device *dev, int idx, uint32_t base,
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uint32_t mask)
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{
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uint32_t base_k, size_k;
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/* Bits 28:0 encode the base address bits 38:10, hence the KiB unit. */
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