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soc/intel/common/block: Don't use device_t in ramstage 

Use of device_t has been abandoned in ramstage.

Change-Id: If2d643eafea854563f56a7f867b7b492b6d09a19
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/28631
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Elyes HAOUAS 2018-09-16 17:35:48 +02:00 committed by Patrick Georgi
parent e1e455bc96
commit 4a13126393
7 changed files with 15 additions and 14 deletions
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4
src/soc/intel/common/block/include/intelblocks/acpi.h
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@ -42,7 +42,7 @@ void soc_write_sci_irq_select(uint32_t scis);
* Calls acpi_write_hpet which creates and fills HPET table and * Calls acpi_write_hpet which creates and fills HPET table and
* adds it to the RSDT (and XSDT) structure. * adds it to the RSDT (and XSDT) structure.
*/ */
unsigned long southbridge_write_acpi_tables(device_t device, unsigned long southbridge_write_acpi_tables(struct device *device,
unsigned long current, unsigned long current,
struct acpi_rsdp *rsdp); struct acpi_rsdp *rsdp);
@ -50,7 +50,7 @@ unsigned long southbridge_write_acpi_tables(device_t device,
* Creates acpi gnvs and adds it to the DSDT table. * Creates acpi gnvs and adds it to the DSDT table.
* GNVS creation is chipset specific and is done in soc specific acpi.c file. * GNVS creation is chipset specific and is done in soc specific acpi.c file.
*/ */
void southbridge_inject_dsdt(device_t device); void southbridge_inject_dsdt(struct device *device);
/* /*
* This function populates the gnvs structure in acpi table. * This function populates the gnvs structure in acpi table.

2
src/soc/intel/common/block/include/intelblocks/graphics.h
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@ -34,7 +34,7 @@ void graphics_soc_init(struct device *dev);
/* /*
* Write ASL entry for Graphics opregion * Write ASL entry for Graphics opregion
* Input: * Input:
* device_t device: device structure * struct device *device: device structure
* current: start address of graphics opregion * current: start address of graphics opregion
* rsdp: pointer to RSDT (and XSDT) structure * rsdp: pointer to RSDT (and XSDT) structure
* *

2
src/soc/intel/common/block/include/intelblocks/mp_init.h
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@ -75,7 +75,7 @@ void get_microcode_info(const void **microcode, int *parallel);
* In this function SOC must perform CPU feature programming * In this function SOC must perform CPU feature programming
* during Ramstage phase. * during Ramstage phase.
*/ */
void soc_core_init(device_t dev); void soc_core_init(struct device *dev);
/* /*
* In this function SOC must fill required mp_ops params, also it * In this function SOC must fill required mp_ops params, also it

6
src/soc/intel/common/block/lpc/lpc.c
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@ -46,7 +46,7 @@ void pch_lpc_add_new_resource(struct device *dev, uint8_t offset,
res->flags = flags; res->flags = flags;
} }
static void pch_lpc_add_io_resources(device_t dev) static void pch_lpc_add_io_resources(struct device *dev)
{ {
/* Add the default claimed legacy IO range for the LPC device. */ /* Add the default claimed legacy IO range for the LPC device. */
pch_lpc_add_new_resource(dev, 0, 0, 0x1000, IORESOURCE_IO | pch_lpc_add_new_resource(dev, 0, 0, 0x1000, IORESOURCE_IO |
@ -56,7 +56,7 @@ static void pch_lpc_add_io_resources(device_t dev)
pch_lpc_soc_fill_io_resources(dev); pch_lpc_soc_fill_io_resources(dev);
} }
static void pch_lpc_read_resources(device_t dev) static void pch_lpc_read_resources(struct device *dev)
{ {
/* Get the PCI resources of this device. */ /* Get the PCI resources of this device. */
pci_dev_read_resources(dev); pci_dev_read_resources(dev);
@ -101,7 +101,7 @@ static void pch_lpc_set_child_resources(struct device *dev)
} }
} }
static void pch_lpc_set_resources(device_t dev) static void pch_lpc_set_resources(struct device *dev)
{ {
pci_dev_set_resources(dev); pci_dev_set_resources(dev);

2
src/soc/intel/common/block/pcie/pcie.c
View File

@ -64,7 +64,7 @@ static void pch_pcie_init(struct device *dev)
pci_write_config16(dev, PCI_SEC_STATUS, reg16); pci_write_config16(dev, PCI_SEC_STATUS, reg16);
} }
static void pcie_set_L1_ss_max_latency(device_t dev, unsigned int offset) static void pcie_set_L1_ss_max_latency(struct device *dev, unsigned int offset)
{ {
/* Set max snoop and non-snoop latency for the SOC */ /* Set max snoop and non-snoop latency for the SOC */
pci_write_config32(dev, offset, pci_write_config32(dev, offset,

8
src/soc/intel/common/block/smbus/smbus.c
View File

@ -22,7 +22,7 @@
#include <soc/smbus.h> #include <soc/smbus.h>
#include "smbuslib.h" #include "smbuslib.h"
static int lsmbus_read_byte(device_t dev, u8 address) static int lsmbus_read_byte(struct device *dev, u8 address)
{ {
u16 device; u16 device;
struct resource *res; struct resource *res;
@ -33,7 +33,7 @@ static int lsmbus_read_byte(device_t dev, u8 address)
return smbus_read8(res->base, device, address); return smbus_read8(res->base, device, address);
} }
static int lsmbus_write_byte(device_t dev, u8 address, u8 data) static int lsmbus_write_byte(struct device *dev, u8 address, u8 data)
{ {
u16 device; u16 device;
struct resource *res; struct resource *res;
@ -50,7 +50,7 @@ static struct smbus_bus_operations lops_smbus_bus = {
.write_byte = lsmbus_write_byte, .write_byte = lsmbus_write_byte,
}; };
static void pch_smbus_init(device_t dev) static void pch_smbus_init(struct device *dev)
{ {
struct resource *res; struct resource *res;
@ -64,7 +64,7 @@ static void pch_smbus_init(device_t dev)
outb(SMBUS_SLAVE_ADDR, res->base + SMB_RCV_SLVA); outb(SMBUS_SLAVE_ADDR, res->base + SMB_RCV_SLVA);
} }
static void smbus_read_resources(device_t dev) static void smbus_read_resources(struct device *dev)
{ {
struct resource *res = new_resource(dev, PCI_BASE_ADDRESS_4); struct resource *res = new_resource(dev, PCI_BASE_ADDRESS_4);
res->base = SMBUS_IO_BASE; res->base = SMBUS_IO_BASE;

5
src/soc/intel/common/block/systemagent/systemagent.c
View File

@ -88,7 +88,7 @@ static const struct sa_mem_map_descriptor sa_memory_map[MAX_MAP_ENTRIES] = {
}; };
/* Read DRAM memory map register value through PCI configuration space */ /* Read DRAM memory map register value through PCI configuration space */
static void sa_read_map_entry(device_t dev, static void sa_read_map_entry(struct device *dev,
const struct sa_mem_map_descriptor *entry, uint64_t *result) const struct sa_mem_map_descriptor *entry, uint64_t *result)
{ {
uint64_t value = 0; uint64_t value = 0;
@ -213,7 +213,8 @@ static bool is_imr_enabled(uint32_t imr_base_reg)
return !!(imr_base_reg & (1 << 31)); return !!(imr_base_reg & (1 << 31));
} }
static void imr_resource(device_t dev, int idx, uint32_t base, uint32_t mask) static void imr_resource(struct device *dev, int idx, uint32_t base,
uint32_t mask)
{ {
uint32_t base_k, size_k; uint32_t base_k, size_k;
/* Bits 28:0 encode the base address bits 38:10, hence the KiB unit. */ /* Bits 28:0 encode the base address bits 38:10, hence the KiB unit. */