rockchip/rk3288: Add 1416MHz as an option for RK3288 APLL

BUG=chrome-os-partner:42054
BRANCH=none
TEST=tested with subsequent patch

Change-Id: I92d67ff4b706c16677661ead1edd5c190ccc6d95
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: dced0fcbc35457d7326d590948ce5fe098a5e735
Original-Signed-off-by: David Hendricks <dhendrix@chromium.org>
Original-Change-Id: I7b29c647380046ac41a290b19fdfba186bcb2127
Original-Reviewed-on: https://chromium-review.googlesource.com/302632
Reviewed-on: http://review.coreboot.org/12136
Tested-by: build bot (Jenkins)
Reviewed-by: David Hendricks <dhendrix@chromium.org>

src/soc/rockchip/rk3288/clock.c

@@ -78,10 +78,12 @@ static const struct pll_div cpll_init_cfg = PLL_DIVISORS(CPLL_HZ, 1, 2);
 
 /* See linux/drivers/clk/rockchip/clk-rk3288.c for more APLL combinations */
 static const struct pll_div apll_1800_cfg = PLL_DIVISORS(1800*MHz, 1, 1);
+static const struct pll_div apll_1416_cfg = PLL_DIVISORS(1416*MHz, 1, 1);
 static const struct pll_div apll_1392_cfg = PLL_DIVISORS(1392*MHz, 1, 1);
 static const struct pll_div apll_600_cfg = PLL_DIVISORS(600*MHz, 1, 2);
 static const struct pll_div *apll_cfgs[] = {
 	[APLL_1800_MHZ] = &apll_1800_cfg,
+	[APLL_1416_MHZ] = &apll_1416_cfg,
 	[APLL_1392_MHZ] = &apll_1392_cfg,
 	[APLL_600_MHZ] = &apll_600_cfg,
 };

src/soc/rockchip/rk3288/include/soc/clock.h

@@ -30,6 +30,7 @@
 
 enum apll_frequencies {
 	APLL_1800_MHZ,
+	APLL_1416_MHZ,
 	APLL_1392_MHZ,
 	APLL_600_MHZ,
 };