skylake: ACPI: Remove Configurable TDP support code
Remove the CTDP support code that is in ACPI. It has been ported from haswell and while the MCHBAR register interface does seem to still exist the calculations for determining PL2 is no longer straightforward. Additionally nothing is using this interface and the expectation is that DPTF will be used for throttling with PL[1234] and having ACPI interfere with the configuration would not be good. BUG=chrome-os-partner:44622 BRANCH=none TEST=emerge-glados coreboot Change-Id: I81e356ddf564a5253458b82bc3327bfb573ab16d Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 884ee9a764bad0b3b4bcaeb5a3f46c5f090a116c Original-Change-Id: I284ab52a305cee25c88df5228b01ff1e9544efe3 Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/302166 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/11719 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
This commit is contained in:
Duncan Laurie
Patrick Georgi
parent
36ad827b68
commit
4a399c2bae
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@ -1,239 +0,0 @@
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/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2014 Google Inc.
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* Copyright (C) 2015 Intel Corporation.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc.
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*/
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Scope (\_SB.PCI0.MCHC)
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{
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Mutex (CTCM, 1) /* CTDP Switch Mutex (sync level 1) */
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Name (CTCC, 0) /* CTDP Current Selection */
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Name (CTCN, 0) /* CTDP Nominal Select */
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Name (CTCD, 1) /* CTDP Down Select */
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Name (CTCU, 2) /* CTDP Up Select */
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Name (SPL1, 0) /* Saved PL1 value */
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OperationRegion (MCHB, SystemMemory,
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Add (MCH_BASE_ADDRESS, 0x5000), 0x1000)
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Field (MCHB, DWordAcc, Lock, Preserve)
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{
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Offset (0x930), /* PACKAGE_POWER_SKU */
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CTDN, 15, /* CTDP Nominal PL1 */
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Offset (0x938), /* PACKAGE_POWER_SKU_UNIT */
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PUNI, 4, /* Power Units */
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, 4,
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EUNI, 5, /* Energy Units */
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, 3,
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TUNI, 4, /* Time Units */
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Offset (0x958), /* PLATFORM_INFO */
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, 32,
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LPMS, 1, /* LPM Support */
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CTNL, 2, /* Config TDP Number level */
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, 5,
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LFM_, 8, /* Maximum Efficiency Ratio (LFM) */
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Offset (0x9a0), /* TURBO_POWER_LIMIT1 */
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PL1V, 15, /* Power Limit 1 Value */
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PL1E, 1, /* Power Limit 1 Enable */
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PL1C, 1, /* Power Limit 1 Clamp */
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PL1T, 7, /* Power Limit 1 Time */
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Offset (0x9a4), /* TURBO_POWER_LIMIT2 */
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PL2V, 15, /* Power Limit 2 Value */
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PL2E, 1, /* Power Limit 2 Enable */
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PL2C, 1, /* Power Limit 2 Clamp */
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PL2T, 7, /* Power Limit 2 Time */
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Offset (0xf3c), /* CONFIG_TDP_NOMINAL */
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TARN, 8, /* CTDP Nominal Turbo Activation Ratio */
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Offset (0xf40), /* CONFIG_TDP_LEVEL1 */
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CTDD, 15, /* CTDP Down PL1 */
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, 1,
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TARD, 8, /* CTDP Down Turbo Activation Ratio */
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Offset (0xf48), /* MSR_CONFIG_TDP_LEVEL2 */
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CTDU, 15, /* CTDP Up PL1 */
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, 1,
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TARU, 8, /* CTDP Up Turbo Activation Ratio */
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Offset (0xf50), /* CONFIG_TDP_CONTROL */
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CTCS, 2, /* CTDP Select */
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Offset (0xf54), /* TURBO_ACTIVATION_RATIO */
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TARS, 8, /* Turbo Activation Ratio Select */
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}
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/*
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* Search CPU0 _PSS looking for control=arg0 and then
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* return previous P-state entry number for new _PPC
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*
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* Format of _PSS:
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* Name (_PSS, Package () {
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* Package (6) { freq, power, tlat, blat, control, status }
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* }
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*/
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External (\_PR.CP00._PSS)
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Method (PSSS, 1, NotSerialized)
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{
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Store (One, Local0) /* Start at P1 */
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Store (SizeOf (\_PR.CP00._PSS), Local1)
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While (LLess (Local0, Local1)) {
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/* Store _PSS entry Control value to Local2 */
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ShiftRight (DeRefOf (Index (DeRefOf (Index
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(\_PR.CP00._PSS, Local0)), 4)), 8, Local2)
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If (LEqual (Local2, Arg0)) {
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Return (Subtract (Local0, 1))
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}
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Increment (Local0)
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}
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Return (0)
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}
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/* Calculate PL2 based on chip type */
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Method (CPL2, 1, NotSerialized)
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{
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Return (Multiply (25, 8))
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}
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/* Set Config TDP Down */
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Method (STND, 0, Serialized)
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{
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If (Acquire (CTCM, 100)) {
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Return (0)
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}
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If (LEqual (CTCD, CTCC)) {
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Release (CTCM)
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Return (0)
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}
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Store ("Set TDP Down", Debug)
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/* Set CTC */
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Store (CTCD, CTCS)
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/* Set TAR */
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Store (TARD, TARS)
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/* Set PPC limit and notify OS */
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Store (PSSS (TARD), PPCM)
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PPCN ()
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/* Set PL2 */
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Store (CPL2 (CTDD), PL2V)
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/* Set PL1 */
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Store (CTDD, PL1V)
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/* Store the new TDP Down setting */
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Store (CTCD, CTCC)
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Release (CTCM)
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Return (1)
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}
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/* Set Config TDP Nominal from Down */
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Method (STDN, 0, Serialized)
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{
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If (Acquire (CTCM, 100)) {
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Return (0)
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}
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If (LEqual (CTCN, CTCC)) {
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Release (CTCM)
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Return (0)
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}
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Store ("Set TDP Nominal", Debug)
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/* Set PL1 */
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Store (CTDN, PL1V)
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/* Set PL2 */
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Store (CPL2 (CTDN), PL2V)
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/* Set PPC limit and notify OS */
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Store (PSSS (TARN), PPCM)
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PPCN ()
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/* Set TAR */
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Store (TARN, TARS)
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/* Set CTC */
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Store (CTCN, CTCS)
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/* Store the new TDP Nominal setting */
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Store (CTCN, CTCC)
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Release (CTCM)
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Return (1)
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}
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/* Calculate PL1 value based on requested TDP */
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Method (TDPP, 1, NotSerialized)
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{
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Return (Multiply (ShiftLeft (Subtract (PUNI, 1), 2), Arg0))
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}
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/* Enable Controllable TDP to limit PL1 to requested value */
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Method (CTLE, 1, Serialized)
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{
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If (Acquire (CTCM, 100)) {
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Return (0)
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}
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Store ("Enable PL1 Limit", Debug)
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/* Set _PPC to LFM */
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Store (PSSS (LFM_), Local0)
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Add (Local0, 1, PPCM)
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\PPCN ()
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/* Set TAR to LFM-1 */
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Subtract (LFM_, 1, TARS)
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/* Set PL1 to desired value */
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Store (PL1V, SPL1)
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Store (TDPP (Arg0), PL1V)
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/* Set PL1 CLAMP bit */
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Store (One, PL1C)
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Release (CTCM)
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Return (1)
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}
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/* Disable Controllable TDP */
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Method (CTLD, 0, Serialized)
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{
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If (Acquire (CTCM, 100)) {
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Return (0)
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}
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Store ("Disable PL1 Limit", Debug)
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/* Clear PL1 CLAMP bit */
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Store (Zero, PL1C)
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/* Set PL1 to normal value */
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Store (SPL1, PL1V)
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/* Set TAR to 0 */
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Store (Zero, TARS)
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/* Set _PPC to 0 */
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Store (Zero, PPCM)
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\PPCN ()
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Release (CTCM)
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Return (1)
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}
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}
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@ -374,6 +374,3 @@ Device (PDRC)
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/* PCI IRQ assignment */
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#include "pci_irqs.asl"
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/* Configurable TDP */
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#include "ctdp.asl"
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