From 4a3e7dd31d090272d2b11bb8c48aa8bad09a3760 Mon Sep 17 00:00:00 2001
From: Marc Jones <marcjones@sysproconsulting.com>
Date: Sun, 23 May 2021 12:17:54 -0600
Subject: [PATCH] src/mainboard/ocp/monolake: Set end of post GPIO

Set the end of post GPIO to the BMC. This gets IPMI working on the BMC.

Change-Id: I1a0055cdfd4a973b5f42570723bd95f1844dd9a7
Signed-off-by: Marc Jones <marcjones@sysproconsulting.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/54880
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
---
 src/mainboard/ocp/monolake/mainboard.c | 12 ++++++++++++
 1 file changed, 12 insertions(+)

diff --git a/src/mainboard/ocp/monolake/mainboard.c b/src/mainboard/ocp/monolake/mainboard.c
index 5f3408ec77..7887bae5c4 100644
--- a/src/mainboard/ocp/monolake/mainboard.c
+++ b/src/mainboard/ocp/monolake/mainboard.c
@@ -14,6 +14,7 @@
  * GNU General Public License for more details.
  */
 
+#include <bootstate.h>
 #include <device/device.h>
 #include <pc80/mc146818rtc.h>
 #include <cf9_reset.h>
@@ -22,6 +23,7 @@
 #include <drivers/vpd/vpd.h>
 #include <console/console.h>
 #include <drivers/ipmi/ipmi_ops.h>
+#include <gpio.h>
 #include "ipmi.h"
 /* VPD variable for enabling/disabling FRB2 timer. */
 #define FRB2_TIMER "FRB2_TIMER"
@@ -232,3 +234,13 @@ const char *smbios_mainboard_serial_number(void)
 	else
 		return CONFIG_MAINBOARD_SERIAL_NUMBER;
 }
+
+/* Set the BMC BIOS POST complete GPIO (FM_BIOS_POST_CMPLT_N) on payload load. */
+static void bmc_set_post_complete_gpio_callback(void *arg)
+{
+	/* GPIO 46 FM_BIOS_POST_CMPLT_N */
+	gpio_set(46, 0);
+	printk(BIOS_DEBUG, "BMC: POST complete gpio set\n");
+}
+
+BOOT_STATE_INIT_ENTRY(BS_PAYLOAD_BOOT, BS_ON_ENTRY, bmc_set_post_complete_gpio_callback, NULL);