src/soc/intel/alderlake: Add PsysPmax setting
This patch feeds PsysPmax setting to FSP through UPD and adds a PsysPmax member in chip information so that we can set PsysPmax through devicetree. The PsysPmax needs to be set correctly mapping to maximum system power. Otherwise, system performance would be limited due to the default PsysPmax setting in FSP is only 21W. BUG=b:193864533, b:195615830 TEST=Set PsysPmax to an example value eg 145 in devicetree && put debug code in FSP to print the PsysPmax value before sending to Pcode, ensure the setting is correctly programmed. Change-Id: Ia07aa815f90739240f110cab984068237c02d896 Signed-off-by: Ryan Lin <ryan.lin@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/58008 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
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@ -492,6 +492,9 @@ struct soc_intel_alderlake_config {
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POWER_CYCLE_DURATION_3S,
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POWER_CYCLE_DURATION_3S,
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POWER_CYCLE_DURATION_4S,
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POWER_CYCLE_DURATION_4S,
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} pch_reset_power_cycle_duration;
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} pch_reset_power_cycle_duration;
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/* Platform Power Pmax */
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uint16_t PsysPmax;
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};
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};
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typedef struct soc_intel_alderlake_config config_t;
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typedef struct soc_intel_alderlake_config config_t;
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@ -652,6 +652,13 @@ static void fill_fsps_misc_power_params(FSP_S_CONFIG *s_cfg,
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s_cfg->PchPmSlpS3MinAssert,
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s_cfg->PchPmSlpS3MinAssert,
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s_cfg->PchPmSlpAMinAssert,
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s_cfg->PchPmSlpAMinAssert,
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power_cycle_duration);
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power_cycle_duration);
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/* Set PsysPmax if it is available from DT */
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if (config->PsysPmax) {
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printk(BIOS_DEBUG, "PsysPmax = %dW\n", config->PsysPmax);
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/* PsysPmax is in unit of 1/8 Watt */
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s_cfg->PsysPmax = config->PsysPmax * 8;
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}
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}
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}
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static void fill_fsps_irq_params(FSP_S_CONFIG *s_cfg,
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static void fill_fsps_irq_params(FSP_S_CONFIG *s_cfg,
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