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soc/intel/common/acpi: Create helper APIs for common P2SB access 

This patch creates a helper library to migrate all the common P2SB
access routines. The PCH P2SB ACPI implementation will now rely on the
common library to perform PCR read/write operations. This will make the
code more modular and easier to maintain.

The helper library provides a single interface for accessing P2SB
registers. This makes it easier to port the code to different platforms,
for example: adding support for PS2B belongs to the IOE die for
Meteor Lake SoC generation.

BUG=b:290856936
TEST=Able to build and boot google/rex.

Change-Id: I0b2e7ea416ca7082f68d0b822ebb9a87025b4a8b
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76408
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Subrata Banik 2023-07-12 09:52:01 +05:30
parent 8554954f9c
commit 4a53ba738d
2 changed files with 103 additions and 36 deletions
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43
src/soc/intel/common/acpi/pch_pcr.asl
View File

@ -1,6 +1,8 @@
/* SPDX-License-Identifier: GPL-2.0-only */
#include <intelblocks/pcr.h>
#include "pcrlib.asl"
/* APIs to access P2SB inside PCH/SoC die */
/*
* Calculate PCR register base at specified PID
@ -8,7 +10,7 @@
*/
Method (PCRB, 1, NotSerialized)
{
Return (CONFIG_PCR_BASE_ADDRESS + (Arg0 << PCR_PORTID_SHIFT))
Return (GPCR(PCH_P2SB, Arg0))
}
/*
@ -18,12 +20,7 @@ Method (PCRB, 1, NotSerialized)
*/
Method (PCRR, 2, Serialized)
{
OperationRegion (PCRD, SystemMemory, PCRB (Arg0) + Arg1, 4)
Field (PCRD, DWordAcc, NoLock, Preserve)
{
DATA, 32
}
Return (DATA)
Return (RPCR(PCH_P2SB, Arg0, Arg1))
}
/*
@ -34,20 +31,7 @@ Method (PCRR, 2, Serialized)
*/
Method (PCRA, 3, Serialized)
{
OperationRegion (PCRD, SystemMemory, PCRB (Arg0) + Arg1, 4)
Field (PCRD, DWordAcc, NoLock, Preserve)
{
DATA, 32
}
DATA &= Arg2
/*
* After every write one needs to read an innocuous register
* to ensure the writes are completed for certain ports. This is done
* for all ports so that the callers don't need the per-port knowledge
* for each transaction.
*/
PCRR (Arg0, Arg1)
APCR(PCH_P2SB, Arg0, Arg1, Arg2)
}
/*
@ -58,18 +42,5 @@ Method (PCRA, 3, Serialized)
*/
Method (PCRO, 3, Serialized)
{
OperationRegion (PCRD, SystemMemory, PCRB (Arg0) + Arg1, 4)
Field (PCRD, DWordAcc, NoLock, Preserve)
{
DATA, 32
}
DATA |= Arg2
/*
* After every write one needs to read an innocuous register
* to ensure the writes are completed for certain ports. This is done
* for all ports so that the callers don't need the per-port knowledge
* for each transaction.
*/
PCRR (Arg0, Arg1)
OPCR(PCH_P2SB, Arg0, Arg1, Arg2)
}

96
src/soc/intel/common/acpi/pcrlib.asl Normal file
View File

@ -0,0 +1,96 @@
/* SPDX-License-Identifier: GPL-2.0-only */
#ifndef _SOC_INTEL_ACPI_PCR_LIB_
#define _SOC_INTEL_ACPI_PCR_LIB_
/* Port Id lives in bits 23:16 and register offset lives in 15:0 of address. */
#define PCR_PORTID_SHIFT 16
/* Die Index */
#define PCH_P2SB 0x00
/* TODO: Add index for P2SB which belongs to IOE Die" */
/*
* Get PCR register base for specified Die at given PID
* Arg0 - Die Index
* Arg1 - PCR Port ID
*/
Method (GPCR, 2, NotSerialized)
{
if (Arg0 == PCH_P2SB) {
Local0 = CONFIG_PCR_BASE_ADDRESS;
} else {
Printf ("Invalid Die index (%o)\n", Arg0)
Return (0)
}
Return (Local0 + (Arg1 << PCR_PORTID_SHIFT))
}
/*
* Read PCR register for specified Die at PID and offset
* Arg0 - Die Index
* Arg1 - PCR Port ID
* Arg2 - Register Offset
*/
Method (RPCR, 3, Serialized)
{
OperationRegion (PCRD, SystemMemory, GPCR (Arg0, Arg1) + Arg2, 4)
Field (PCRD, DWordAcc, NoLock, Preserve)
{
DATA, 32
}
Return (DATA)
}
/*
* Perform PCR register AND for specified Die at PID and offset
* Arg0 - Die Index
* Arg1 - PCR Port ID
* Arg2 - Register Offset
* Arg3 - Value to AND
*/
Method (APCR, 4, Serialized)
{
OperationRegion (PCRD, SystemMemory, GPCR (Arg0, Arg1) + Arg2, 4)
Field (PCRD, DWordAcc, NoLock, Preserve)
{
DATA, 32
}
DATA &= Arg3
/*
* After every write one needs to read an innocuous register
* to ensure the writes are completed for certain ports. This is done
* for all ports so that the callers don't need the per-port knowledge
* for each transaction.
*/
RPCR (Arg0, Arg1, Arg2)
}
/*
* Perform PCR register OR for specified Die at PID and offset
* Arg0 - Die Index
* Arg1 - PCR Port ID
* Arg2 - Register Offset
* Arg3 - Value to OR
*/
Method (OPCR, 4, Serialized)
{
OperationRegion (PCRD, SystemMemory, GPCR (Arg0, Arg1) + Arg2, 4)
Field (PCRD, DWordAcc, NoLock, Preserve)
{
DATA, 32
}
DATA |= Arg3
/*
* After every write one needs to read an innocuous register
* to ensure the writes are completed for certain ports. This is done
* for all ports so that the callers don't need the per-port knowledge
* for each transaction.
*/
RPCR (Arg0, Arg1, Arg2)
}
#endif /* _SOC_INTEL_ACPI_PCR_LIB_ */