GNUBoot
/
coreboot-kgpe-d16
2
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

soc/intel/alderlake: Hook up UPD PchHdaSdiEnable 

Hook the PchHdaSdiEnable UPD so that mainboard can change the
settings via devicetree. PchHdaSdiEnable UPD enable HDA SDI lanes.

BUG=b:268546941
TEST=Verified the settings on google/brya using debug FSP logs.

Signed-off-by: Bora Guvendik <bora.guvendik@intel.com>
Change-Id: I82bbfa5442936aefa53f8826e395b7ce75c895a3
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76449
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
This commit is contained in:
Bora Guvendik 2023-07-13 14:01:40 -07:00 committed by Felix Held
parent 0572d557ac
commit 4a58d14506
2 changed files with 6 additions and 0 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

3
src/soc/intel/alderlake/chip.h
View File

@ -23,6 +23,8 @@
/* Define config parameters for In-Band ECC (IBECC). */
#define MAX_IBECC_REGIONS 8
#define MAX_HD_AUDIO_SDI_LINKS 2
/* In-Band ECC Operation Mode */
enum ibecc_mode {
IBECC_MODE_PER_REGION,
@ -413,6 +415,7 @@ struct soc_intel_alderlake_config {
/* Audio related */
uint8_t pch_hda_audio_link_hda_enable;
uint8_t pch_hda_dsp_enable;
bool pch_hda_sdi_enable[MAX_HD_AUDIO_SDI_LINKS];
/* iDisp-Link T-Mode 0: 2T, 2: 4T, 3: 8T, 4: 16T */
enum {

3
src/soc/intel/alderlake/romstage/fsp_params.c
View File

@ -250,6 +250,9 @@ static void fill_fspm_audio_params(FSP_M_CONFIG *m_cfg,
memset(m_cfg->PchHdaAudioLinkDmicEnable, 0, sizeof(m_cfg->PchHdaAudioLinkDmicEnable));
memset(m_cfg->PchHdaAudioLinkSspEnable, 0, sizeof(m_cfg->PchHdaAudioLinkSspEnable));
memset(m_cfg->PchHdaAudioLinkSndwEnable, 0, sizeof(m_cfg->PchHdaAudioLinkSndwEnable));
#if CONFIG(SOC_INTEL_RAPTORLAKE)
memcpy(m_cfg->PchHdaSdiEnable, config->pch_hda_sdi_enable, sizeof(m_cfg->PchHdaSdiEnable));
#endif
}
static void fill_fspm_ish_params(FSP_M_CONFIG *m_cfg,