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src/soc: Add required space before opening parenthesis '(' 

Change-Id: Ifc47f103492a2cd6c818dfd64be971d34afbe0a4
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/16324
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
This commit is contained in:
Elyes HAOUAS 2016-08-25 21:07:59 +02:00 committed by Martin Roth
parent 3c80408fc8
commit 4a83f1cf24
19 changed files with 351 additions and 351 deletions
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112
src/soc/broadcom/cygnus/ddr_init.c
View File

@ -315,7 +315,7 @@ int cygnus_phy_powerup(void)
data = reg32_read((volatile uint32_t *)CRMU_DDR_PHY_AON_CTRL);
if(reg32_read((volatile uint32_t *)CRMU_IHOST_POR_WAKEUP_FLAG)==0)
if (reg32_read((volatile uint32_t *)CRMU_IHOST_POR_WAKEUP_FLAG)==0)
{
/* Step 1: POWRON */
data = reg32_read((volatile uint32_t *)CRMU_DDR_PHY_AON_CTRL);
@ -328,7 +328,7 @@ int cygnus_phy_powerup(void)
data |= 0x10;// assert power OK
reg32_write((volatile uint32_t *)CRMU_DDR_PHY_AON_CTRL, data);
while(count--)
while (count--)
__udelay(2);
}
@ -350,10 +350,10 @@ int cygnus_phy_powerup(void)
reg32_write((volatile uint32_t *)CRMU_DDR_PHY_AON_CTRL, data);
count = 20;
while(count--)
while (count--)
__udelay(2);
if(reg32_read((volatile uint32_t *)CRMU_IHOST_POR_WAKEUP_FLAG)==0)
if (reg32_read((volatile uint32_t *)CRMU_IHOST_POR_WAKEUP_FLAG)==0)
{
/* Step 5: release reset */
data |= 0x20;// de-assert reset
@ -363,7 +363,7 @@ int cygnus_phy_powerup(void)
{
printk(BIOS_INFO, "DeepSleep wakeup: ddr phy init bypassed 2\n");
}
while((reg32_read((volatile uint32_t *)DDR_S1_IDM_IO_STATUS) & 0x08) != 0x08) {
while ((reg32_read((volatile uint32_t *)DDR_S1_IDM_IO_STATUS) & 0x08) != 0x08) {
//poll DDR_S1_IDM_IO_STATUS__o_phy_pwrup_rsb
}
@ -381,14 +381,14 @@ void dump_phy_regs(void)
{
int i;
printk(BIOS_DEBUG, "\n PHY register dump: Control registers\n");
for(i = 0; i <= 0x94; i+=4)
for (i = 0; i <= 0x94; i+=4)
{
printk(BIOS_DEBUG, "0x%03x,\t0x%08x,\n", i,
*(volatile uint32_t *)(DDR_PHY_CONTROL_REGS_REVISION + i));
}
printk(BIOS_DEBUG, "\n PHY register dump: Wordlane0 registers\n");
for(i = 0; i <= 0xc5; i+=4)
for (i = 0; i <= 0xc5; i+=4)
{
printk(BIOS_DEBUG, "0x%03x,\t0x%08x,\n", i,
*(volatile uint32_t *)(DDR_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQS_P + i));
@ -402,7 +402,7 @@ void ddr_init_regs(unsigned int * tblptr)
unsigned int offset = *tblptr;
unsigned int *addr = (unsigned int *)DDR_DENALI_CTL_00;
while(offset != 0xffffffff) {
while (offset != 0xffffffff) {
++tblptr;
#if __BYTE_ORDER__ == __ORDER_LITTLE_ENDIAN__
addr[offset] = *tblptr;
@ -420,7 +420,7 @@ void ddr_phy_ctl_regs_ovrd(unsigned int * tblptr)
unsigned int *addr = (unsigned int *)DDR_PHY_CONTROL_REGS_REVISION;
unsigned int val;
while(offset != 0xffffffff) {
while (offset != 0xffffffff) {
++tblptr;
#if __BYTE_ORDER__ == __ORDER_LITTLE_ENDIAN__
addr[offset/4] = *tblptr;
@ -459,7 +459,7 @@ int ReWriteModeRegisters( void )
break;
}
--j;
} while( j );
} while ( j );
if ( j == 0 && (reg32_read( (volatile uint32_t *)DDR_DENALI_CTL_89) & (1 << 18) ) == 0 ) {
printk(BIOS_ERR, "Error: DRAM mode registers write failed\n");
@ -512,7 +512,7 @@ static int simple_memory_test(void *start, uint32_t len)
paddr = (volatile uint32_t *)start;
rand_c_value = RAND_C_INIT;
rand_t_value = RAND_T_INIT;
for(i=0; i<len; i++, paddr++) {
for (i=0; i<len; i++, paddr++) {
rand_c_value *= RAND_MAGIC_3;
rand_t_value ^= rand_t_value >> 15;
rand_t_value ^= rand_t_value << 17;
@ -523,7 +523,7 @@ static int simple_memory_test(void *start, uint32_t len)
paddr = (volatile uint32_t *)start;
rand_c_value = RAND_C_INIT;
rand_t_value = RAND_T_INIT;
for(i=0; i<len; i++, paddr++) {
for (i=0; i<len; i++, paddr++) {
rand_c_value *= RAND_MAGIC_3;
rand_t_value ^= rand_t_value >> 15;
rand_t_value ^= rand_t_value << 17;
@ -726,7 +726,7 @@ static int write_shmoo_to_flash(void *buf, int length)
/* Check if erasing is required */
flptr = (volatile uint32_t *)(IPROC_QSPI_MEM_BASE + offset / 4 * 4);
j = (length - 1) / 4 + 1;
for(i=0; i<j; i++, flptr++) {
for (i=0; i<j; i++, flptr++) {
if (*flptr != 0xFFFFFFFF) {
erase = 1;
break;
@ -785,7 +785,7 @@ static int write_shmoo_to_flash(void *buf, int length)
flptr = (volatile uint32_t *)(IPROC_NOR_MEM_BASE + offset / 4 * 4);
shmoo_start = flptr;
j = (length - 1) / 4 + 1;
for(i=0; i<j; i++, flptr++) {
for (i=0; i<j; i++, flptr++) {
if (*flptr != 0xFFFFFFFF) {
erase = 1;
break;
@ -902,7 +902,7 @@ static volatile uint32_t *validate_flash_shmoo_values(struct shmoo_signature *ps
return NULL;
}
chksum = 0;
for(i=0; i<length * 2; i++, ptr++) {
for (i=0; i<length * 2; i++, ptr++) {
chksum += *ptr;
}
if (chksum != checksum) {
@ -937,13 +937,13 @@ static int try_restore_shmoo(void)
unsigned long start;
printk(BIOS_INFO, "Press Ctrl-C to run Shmoo ..... ");
start = get_timer(0);
while(get_timer(start) <= CONFIG_SHMOO_REUSE_DELAY_MSECS) {
while (get_timer(start) <= CONFIG_SHMOO_REUSE_DELAY_MSECS) {
if (tstc()) {
c = getc();
if (c == 0x03) {
printk(BIOS_INFO, "Pressed.\n");
printk(BIOS_INFO, "Do you want to run the Shmoo? [y/N] ");
for(;;) {
for (;;) {
c = getc();
if (c == 'y' || c == 'Y') {
printk(BIOS_INFO, "Y\n");
@ -972,10 +972,10 @@ static int try_restore_shmoo(void)
/* Restore values from flash */
printk(BIOS_INFO, "Restoring Shmoo parameters from flash ..... ");
flptr += 5;
for(i=0; i<pairs; i++) {
for (i=0; i<pairs; i++) {
reg = (uint32_t *)(*flptr++);
val = (uint32_t *)(*flptr++);
if( (((uint32_t)reg >= DDR_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE_RD_EN) && ((uint32_t)reg <= (DDR_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE_RD_EN + 0x114)))
if ( (((uint32_t)reg >= DDR_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE_RD_EN) && ((uint32_t)reg <= (DDR_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE_RD_EN + 0x114)))
#if (CONFIG_CYGNUS_SHMOO_REUSE_DDR_32BIT || defined(CONFIG_NS_PLUS))
|| (((uint32_t)reg >= DDR_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE_RD_EN) && ((uint32_t)reg <= (DDR_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE_RD_EN + 0x114)))
#endif
@ -1026,7 +1026,7 @@ void iproc_save_shmoo_values(void)
if (flptr != NULL) {
/* Check if the flash data are the same as current DDR PHY values */
flptr += 5;
for(i=0; i<pairs; i++) {
for (i=0; i<pairs; i++) {
reg = *flptr++;
val = *flptr++;
if (val != reg32_read(reg)) {
@ -1060,7 +1060,7 @@ void iproc_save_shmoo_values(void)
/* Copy registers and values to buffer */
chksum = 0;
for(i=0; i<sizeof(ddr_phy_ctl_regs) / sizeof(ddr_phy_ctl_regs[0]); i++) {
for (i=0; i<sizeof(ddr_phy_ctl_regs) / sizeof(ddr_phy_ctl_regs[0]); i++) {
reg = (uint32_t)DDR_PHY_CONTROL_REGS_REVISION + ddr_phy_ctl_regs[i];
*ptr++ = reg;
chksum += reg;
@ -1069,7 +1069,7 @@ void iproc_save_shmoo_values(void)
*ptr++ = val;
chksum += val;
}
for(i=0; i<sizeof(ddr_phy_wl_regs) / sizeof(ddr_phy_wl_regs[0]); i++) {
for (i=0; i<sizeof(ddr_phy_wl_regs) / sizeof(ddr_phy_wl_regs[0]); i++) {
reg = (uint32_t)DDR_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE_RD_EN + ddr_phy_wl_regs[i];
*ptr++ = reg;
chksum += reg;
@ -1080,7 +1080,7 @@ void iproc_save_shmoo_values(void)
}
#if (CONFIG_CYGNUS_SHMOO_REUSE_DDR_32BIT || defined(CONFIG_NS_PLUS))
if (is_ddr_32bit()) {
for(i=0; i<sizeof(ddr_phy_wl_regs) / sizeof(ddr_phy_wl_regs[0]); i++) {
for (i=0; i<sizeof(ddr_phy_wl_regs) / sizeof(ddr_phy_wl_regs[0]); i++) {
reg = (uint32_t)DDR_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE_RD_EN + ddr_phy_wl_regs[i];
*ptr++ = reg;
chksum += reg;
@ -1092,7 +1092,7 @@ void iproc_save_shmoo_values(void)
}
#endif /* (CONFIG_CYGNUS_SHMOO_REUSE_DDR_32BIT || defined(CONFIG_NS_PLUS)) */
#ifdef CONFIG_IPROC_DDR_ECC
for(i=0; i<sizeof(ddr_phy_eccl_regs) / sizeof(ddr_phy_eccl_regs[0]); i++) {
for (i=0; i<sizeof(ddr_phy_eccl_regs) / sizeof(ddr_phy_eccl_regs[0]); i++) {
reg = (uint32_t)DDR_DENALI_CTL_00 + ddr_phy_eccl_regs[i];
*ptr++ = reg;
chksum += reg;
@ -1128,7 +1128,7 @@ static int clear_ddr(uint32_t offset, uint32_t size)
reg32_write((uint32_t *)DDR_BistConfig,reg32_read((uint32_t *)DDR_BistConfig) & ~0x1);
for( i = 0; i < 1000; i++);
for ( i = 0; i < 1000; i++);
#if !defined(CONFIG_IPROC_P7)
reg32_write((volatile uint32_t *)DDR_DENALI_CTL_213, 0x00FFFFFF);
@ -1163,21 +1163,21 @@ static int clear_ddr(uint32_t offset, uint32_t size)
reg32_set_bits((volatile uint32_t *)DDR_BistConfigurations, 1 << DDR_BistConfigurations__BistEn);
start = get_timer(0);
while(get_timer(start) <= 10000) {
if(reg32_read((volatile uint32_t *)DDR_BistStatuses) & (1 << DDR_BistStatuses__BistFinished))
while (get_timer(start) <= 10000) {
if (reg32_read((volatile uint32_t *)DDR_BistStatuses) & (1 << DDR_BistStatuses__BistFinished))
break;
}
/* Clear BIST_EN bit */
reg32_clear_bits((volatile uint32_t *)DDR_BistConfigurations, 1 << DDR_BistConfigurations__BistEn);
if((get_timer(start) <= 10000) &&
if ((get_timer(start) <= 10000) &&
(!reg32_read((volatile uint32_t *)DDR_BistErrorOccurred)))
{
printk(BIOS_INFO, "clear_ddr: OK\n");
return(0);
}
printk(BIOS_INFO, "clear_ddr: Failed: 0x%lx\n", get_timer(start));
if(reg32_read((volatile uint32_t *)DDR_BistErrorOccurred))
if (reg32_read((volatile uint32_t *)DDR_BistErrorOccurred))
printk(BIOS_ERR, "clear_ddr: Error occurred\n");
return(1);
}
@ -1198,14 +1198,14 @@ static int simple_ddr_crc32_check(void)
printk(BIOS_INFO, "Checking simple DDR CRC, word start 0x%p, len 0x%08x...\n", buf, len);
for(offset=0; offset<len; offset++)
for (offset=0; offset<len; offset++)
{
crc ^= *buf++;
}
crc_mcu = reg32_read((volatile uint32_t *)0x03012A00);
if(crc != crc_mcu)
if (crc != crc_mcu)
{
printk(BIOS_ERR, "DDR CRC NOT match, old=0x%08x, new=0x%08x!\n", crc_mcu, crc);
return -1;
@ -1230,11 +1230,11 @@ void ddr_init2(void)
uint32_t pwrctli0 = reg32_read((volatile uint32_t *)IHOST_SCU_POWER_STATUS) & 0x3;
skip_shmoo = reg32_read((volatile uint32_t *)CRMU_IHOST_POR_WAKEUP_FLAG) & 0x1;
if(pwrctli0==2)
if (pwrctli0==2)
{
goto wakeup;
}
else if(pwrctli0==3)
else if (pwrctli0==3)
{
skip_shmoo = 1;
reg32_write((volatile uint32_t *)IHOST_GTIM_GLOB_CTRL, reg32_read((volatile uint32_t *)IHOST_GTIM_GLOB_CTRL)| 0x1);
@ -1260,7 +1260,7 @@ void ddr_init2(void)
sku_id = (reg32_read((volatile uint32_t *)ROM_S0_IDM_IO_STATUS) >> 2) & 0x03;
#endif
/* See if it is KATANA2, KATANA2 doesn't have right chip ID in ChipcommonA_ChipID */
if(((sku_id & 0xfff0) == 0xa450) || ((sku_id & 0xfff0) == 0xb450) || sku_id == 0xb248) {
if (((sku_id & 0xfff0) == 0xa450) || ((sku_id & 0xfff0) == 0xb450) || sku_id == 0xb248) {
dev_id = 56450; /* KATANA2 */
}
@ -1290,7 +1290,7 @@ void ddr_init2(void)
printk(BIOS_INFO, "MEMC 0 DDR speed = %dMHz\n", ddr_clk);
status = change_ddr_clock(ddr_clk);
if(status) {
if (status) {
printk(BIOS_INFO, "CRU LCPLL configuratioin failed\n");
goto done;
}
@ -1326,12 +1326,12 @@ void ddr_init2(void)
reg32_write((volatile uint32_t *)CRU_ddrphy_pwr_ctrl, val);
/* Wait for PHY power up */
for(i=0; i < 0x19000; i++) {
for (i=0; i < 0x19000; i++) {
val = reg32_read((volatile uint32_t *)DDR_S1_IDM_IO_STATUS);
if((val & (1 << DDR_S1_IDM_IO_STATUS__o_phy_pwrup_rsb)))
if ((val & (1 << DDR_S1_IDM_IO_STATUS__o_phy_pwrup_rsb)))
break;
}
if(i == 0x19000) {
if (i == 0x19000) {
printk(BIOS_ERR, "DDR PHY not power up\n");
goto done;
}
@ -1347,7 +1347,7 @@ void ddr_init2(void)
/* Set the ddr_ck to 400 MHz, 2x memc clock */
reg32_write_masked((volatile uint32_t *)DDR_S1_IDM_IO_CONTROL_DIRECT, 0xfff << 16, /*ddr_clk*/ 0x190 << 16);
if(pwrctli0==3)
if (pwrctli0==3)
{
printk(BIOS_INFO, "\n PRE_SRX call\n");
PRE_SRX();
@ -1369,13 +1369,13 @@ void ddr_init2(void)
}
/* Wait for PHY ready */
for(i=0; i < 0x19000; i++) {
for (i=0; i < 0x19000; i++) {
val = reg32_read((volatile uint32_t *)DDR_S1_IDM_IO_STATUS);
if((val & (1 << DDR_S1_IDM_IO_STATUS__o_phy_ready)))
if ((val & (1 << DDR_S1_IDM_IO_STATUS__o_phy_ready)))
break; /* DDR PHY is up */
}
if(i == 0x19000) {
if (i == 0x19000) {
printk(BIOS_ERR, "DDR PLL not locked\n");
goto done;
}
@ -1385,21 +1385,21 @@ void ddr_init2(void)
#endif /* defined(CONFIG_IPROC_P7) */
/* Wait for DDR PHY up */
for(i=0; i < 0x19000; i++) {
for (i=0; i < 0x19000; i++) {
val = reg32_read((volatile uint32_t *)DDR_PHY_CONTROL_REGS_REVISION);
if( val != 0) {
if ( val != 0) {
printk(BIOS_INFO, "PHY revision version: 0x%08x\n", val);
break; /* DDR PHY is up */
}
}
if(i == 0x19000) {
if (i == 0x19000) {
printk(BIOS_ERR, "DDR PHY is not up\n");
return;
}
#if IS_ENABLED(CONFIG_SOC_BROADCOM_CYGNUS)
if(!skip_shmoo)
if (!skip_shmoo)
{
printk(BIOS_INFO, "ddr_init2: Calling soc_and28_shmoo_dram_info_set\n");
/* Cygnus clock speed:
@ -1434,10 +1434,10 @@ void ddr_init2(void)
#endif
#if IS_ENABLED(CONFIG_SOC_BROADCOM_CYGNUS)
if(!skip_shmoo)
if (!skip_shmoo)
{
printk(BIOS_INFO, "ddr_init2: Calling soc_and28_shmoo_phy_init\n");
if(soc_and28_shmoo_phy_init(unit, 0) != SOC_E_NONE) {
if (soc_and28_shmoo_phy_init(unit, 0) != SOC_E_NONE) {
printk(BIOS_ERR, "DDR PHY initialization failed\n");
goto done;
@ -1458,7 +1458,7 @@ void ddr_init2(void)
ddr_init_regs(ddr_init_tab);
ddr_type = 1;
if(ddr_type) {
if (ddr_type) {
/* DDR3 */
switch(ddr_clk) {
#ifdef CONFIG_DDR333
@ -1515,9 +1515,9 @@ void ddr_init2(void)
reg32_set_bits((volatile uint32_t *)DDR_DENALI_CTL_00, 0x01);
#if IS_ENABLED(CONFIG_SOC_BROADCOM_CYGNUS)
if(!skip_shmoo)
if (!skip_shmoo)
{
while(!(reg32_read((volatile uint32_t *)DDR_DENALI_CTL_175) & 0x100));
while (!(reg32_read((volatile uint32_t *)DDR_DENALI_CTL_175) & 0x100));
printk(BIOS_INFO, "ddr_init2: MemC initialization complete\n");
reg32_set_bits((unsigned int *)DDR_DENALI_CTL_177, 0x00100);
@ -1607,7 +1607,7 @@ void ddr_init2(void)
#if IS_ENABLED(CONFIG_SOC_BROADCOM_CYGNUS)
/* SRX */
if(skip_shmoo)
if (skip_shmoo)
{
// Enter Self refresh (dummy) , to keep Denali happy
reg32_write((unsigned int *)DDR_DENALI_CTL_56, 0x0a050505);
@ -1629,19 +1629,19 @@ void ddr_init2(void)
// iproc_dump_ddr_regs();
if(pwrctli0==0)
if (pwrctli0==0)
goto done;
wakeup:
printk(BIOS_INFO, "Wakeup from %s\n", pwrctli0==2 ? "SLEEP":"DEEPSLEEP");
if(pwrctli0==3)
if (pwrctli0==3)
{
__udelay(10000);
if(simple_ddr_crc32_check()<0)
if (simple_ddr_crc32_check()<0)
{
printk(BIOS_INFO, "Die...\n");
while(1);
while (1);
}
}

530
src/soc/broadcom/cygnus/shmoo_and28.c
View File

File diff suppressed because it is too large Load Diff

12
src/soc/broadcom/cygnus/ydc_ddr_bist.c
View File

@ -61,11 +61,11 @@ soc_ydc_ddr_bist_config_set(int unit, int phy_ndx, ydc_ddr_bist_info_t *bist_inf
YDC_DDR_BIST_SET_FIELD(data, YDC_DDR_BIST, CONFIGURATIONS, IND_WR_RD_ADDR_MODE, 1);
WRITE_YDC_DDR_BIST_CONFIGURATIONSr(0, YDC_DDR_BIST_REG_BASE, data);
if(!((*bist_info).prbs_mode))
if (!((*bist_info).prbs_mode))
{
if((*bist_info).mpr_mode)
if ((*bist_info).mpr_mode)
{
if(YDC_DDR_BIST_PHY_BITWITDH_IS_32)
if (YDC_DDR_BIST_PHY_BITWITDH_IS_32)
{
WRITE_YDC_DDR_BIST_PATTERN_WORD_0r(0, YDC_DDR_BIST_REG_BASE, 0xFFFFFFFF);
WRITE_YDC_DDR_BIST_PATTERN_WORD_1r(0, YDC_DDR_BIST_REG_BASE, 0x00000000);
@ -128,11 +128,11 @@ soc_ydc_ddr_bist_run(int unit, int phy_ndx, ydc_ddr_bist_err_cnt_t *error_count)
poll_count = 0;
while(TRUE)
while (TRUE)
{
READ_YDC_DDR_BIST_STATUSESr(0, YDC_DDR_BIST_REG_BASE, &data);
if(YDC_DDR_BIST_GET_FIELD(data, YDC_DDR_BIST, STATUSES, BIST_FINISHED))
if (YDC_DDR_BIST_GET_FIELD(data, YDC_DDR_BIST, STATUSES, BIST_FINISHED))
{
READ_YDC_DDR_BIST_CONFIGURATIONSr(0, YDC_DDR_BIST_REG_BASE, &data);
YDC_DDR_BIST_SET_FIELD(data, YDC_DDR_BIST, CONFIGURATIONS, BIST_EN, 0);
@ -140,7 +140,7 @@ soc_ydc_ddr_bist_run(int unit, int phy_ndx, ydc_ddr_bist_err_cnt_t *error_count)
break;
}
if(poll_count > YDC_DDR_BIST_POLL_COUNT_LIMIT)
if (poll_count > YDC_DDR_BIST_POLL_COUNT_LIMIT)
{
READ_YDC_DDR_BIST_CONFIGURATIONSr(0, YDC_DDR_BIST_REG_BASE, &data);
YDC_DDR_BIST_SET_FIELD(data, YDC_DDR_BIST, CONFIGURATIONS, BIST_EN, 0);

2
src/soc/intel/baytrail/pcie.c
View File

@ -197,7 +197,7 @@ static void check_device_present(device_t dev)
reg_script_run_on_dev(dev, no_dev_behind_port);
dev->enabled = 0;
}
} else if(!dev->enabled) {
} else if (!dev->enabled) {
/* Port is disabled, but device present. Disable link. */
pci_write_config32(dev, LCTL,
pci_read_config32(dev, LCTL) | LD);

2
src/soc/intel/baytrail/romstage/early_spi.c
View File

@ -45,7 +45,7 @@ int early_spi_read_wpsr(u8 *sr)
SPI16(SSFC) = DATA_CYCLE | SPI_CYCLE_GO;
/* Wait for error / complete status */
while(timeout--) {
while (timeout--) {
u16 status = SPI16(SSFS);
if (status & FLASH_CYCLE_ERROR) {
printk(BIOS_ERR, "SPI rdsr failed\n");

2
src/soc/intel/baytrail/sata.c
View File

@ -170,7 +170,7 @@ static void sata_enable(device_t dev)
reg16 = pci_read_config16(dev, 0x90);
reg16 &= ~0x03e0;
reg16 |= (config->sata_port_map ^ 0x3) << 8;
if(config->sata_ahci)
if (config->sata_ahci)
reg16 |= 0x60;
pci_write_config16(dev, 0x90, reg16);

4
src/soc/intel/braswell/gpio_support.c
View File

@ -109,7 +109,7 @@ static void gpio_config_pad(gpio_t gpio_num, const struct soc_gpio_map *cfg)
int max_gpio_cnt = GP_SOUTHWEST_COUNT + GP_NORTH_COUNT + GP_EAST_COUNT
+ GP_SOUTHEAST_COUNT;
if(gpio_num > max_gpio_cnt)
if (gpio_num > max_gpio_cnt)
return;
/* Get GPIO Community based on GPIO_NUMBER */
comm = gpio_get_community_num(gpio_num, &pad_num);
@ -149,7 +149,7 @@ int gpio_get(gpio_t gpio_num)
int max_gpio_cnt = GP_SOUTHWEST_COUNT + GP_NORTH_COUNT + GP_EAST_COUNT
+ GP_SOUTHEAST_COUNT;
if(gpio_num > max_gpio_cnt)
if (gpio_num > max_gpio_cnt)
return -1;
/* Get GPIO Community based on GPIO_NUMBER */

2
src/soc/intel/braswell/tsc_freq.c
View File

@ -41,7 +41,7 @@ static const unsigned int cpu_bus_clk_freq_table[] = {
unsigned int cpu_bus_freq_khz(void)
{
msr_t clk_info = rdmsr(MSR_BSEL_CR_OVERCLOCK_CONTROL);
if((clk_info.lo & 0xF) < (sizeof(cpu_bus_clk_freq_table)/sizeof(unsigned int)))
if ((clk_info.lo & 0xF) < (sizeof(cpu_bus_clk_freq_table)/sizeof(unsigned int)))
{
return(cpu_bus_clk_freq_table[clk_info.lo & 0xF]);
}

2
src/soc/intel/broadwell/lpc.c
View File

@ -105,7 +105,7 @@ static void pch_pirq_init(device_t dev)
pci_write_config8(dev, PIRQG_ROUT, config->pirqg_routing);
pci_write_config8(dev, PIRQH_ROUT, config->pirqh_routing);
for(irq_dev = all_devices; irq_dev; irq_dev = irq_dev->next) {
for (irq_dev = all_devices; irq_dev; irq_dev = irq_dev->next) {
u8 int_pin=0, int_line=0;
if (!irq_dev->enabled || irq_dev->path.type != DEVICE_PATH_PCI)

2
src/soc/intel/broadwell/smihandler.c
View File

@ -505,7 +505,7 @@ static void southbridge_smi_monitor(void)
printk(BIOS_DEBUG, " trapped io address = 0x%x\n",
trap_cycle & 0xfffc);
for (i=0; i < 4; i++)
if(IOTRAP(i)) printk(BIOS_DEBUG, " TRAP = %d\n", i);
if (IOTRAP(i)) printk(BIOS_DEBUG, " TRAP = %d\n", i);
printk(BIOS_DEBUG, " AHBE = %x\n", (trap_cycle >> 16) & 0xf);
printk(BIOS_DEBUG, " MASK = 0x%08x\n", mask);
printk(BIOS_DEBUG, " read/write: %s\n",

4
src/soc/intel/common/hda_verb.c
View File

@ -106,7 +106,7 @@ static int hda_wait_for_ready(u8 *base)
int timeout = 50;
while(timeout--) {
while (timeout--) {
u32 reg32 = read32(base + HDA_ICII_REG);
if (!(reg32 & HDA_ICII_BUSY))
return 0;
@ -134,7 +134,7 @@ static int hda_wait_for_valid(u8 *base)
* same duration */
int timeout = 50;
while(timeout--) {
while (timeout--) {
reg32 = read32(base + HDA_ICII_REG);
if ((reg32 & (HDA_ICII_VALID | HDA_ICII_BUSY)) ==
HDA_ICII_VALID)

4
src/soc/intel/fsp_baytrail/southcluster.c
View File

@ -190,7 +190,7 @@ static void write_pci_config_irqs(void)
* the Interrupt Route registers in the ILB
*/
printk(BIOS_DEBUG, "PCI_CFG IRQ: Write PCI config space IRQ assignments\n");
for(irq_dev = all_devices; irq_dev; irq_dev = irq_dev->next) {
for (irq_dev = all_devices; irq_dev; irq_dev = irq_dev->next) {
if ((irq_dev->path.type != DEVICE_PATH_PCI) ||
(!irq_dev->enabled))
@ -287,7 +287,7 @@ static void sc_pirq_init(device_t dev)
write16(ir_base + i, ir->pcidev[i]);
/* If the entry is more than just 0, print it out */
if(ir->pcidev[i]) {
if (ir->pcidev[i]) {
printk(BIOS_SPEW, " %d: ", i);
for (j = 0; j < 4; j++) {
pirq = (ir->pcidev[i] >> (j * 4)) & 0xF;

2
src/soc/intel/quark/i2c.c
View File

@ -162,7 +162,7 @@ int platform_i2c_transfer(unsigned bus, struct i2c_seg *segments, int count)
}
timeout--;
udelay(1);
} while(1);
} while (1);
/* Finish reading the data bytes */
while (read_length > 0) {

6
src/soc/intel/skylake/chip.c
View File

@ -464,17 +464,17 @@ void soc_silicon_init_params(SILICON_INIT_UPD *params)
}
memcpy(params->PxRcConfig, irq_config, PCH_MAX_IRQ_CONFIG);
/* GPIO IRQ Route The valid values is 14 or 15*/
if(config->GpioIrqSelect == 0)
if (config->GpioIrqSelect == 0)
params->GpioIrqRoute = GPIO_IRQ14;
else
params->GpioIrqRoute = config->GpioIrqSelect;
/* SCI IRQ Select The valid values is 9, 10, 11 and 20 21, 22, 23*/
if(config->SciIrqSelect == 0)
if (config->SciIrqSelect == 0)
params->SciIrqSelect = SCI_IRQ9;
else
params->SciIrqSelect = config->SciIrqSelect;
/* TCO IRQ Select The valid values is 9, 10, 11, 20 21, 22, 23*/
if(config->TcoIrqSelect == 0)
if (config->TcoIrqSelect == 0)
params->TcoIrqSelect = TCO_IRQ9;
else
params->TcoIrqSelect = config->TcoIrqSelect;

6
src/soc/mediatek/mt8173/dramc_pi_basic_api.c
View File

@ -99,7 +99,7 @@ static void mem_pll_pre_init(u32 channel)
setbits_le32(&ch[channel].ddrphy_regs->mempll_divider, 0x1 << 24 |
0x1 << 7);
if(channel == CHANNEL_A) {
if (channel == CHANNEL_A) {
/* select memory clock sync for channel A (internal source) */
clrbits_le32(&ch[channel].ddrphy_regs->mempll_divider, 0x1 << 3);
}
@ -292,7 +292,7 @@ static void mem_pll_phase_cali(u32 channel)
/* 7. delay line overflow break */
for (i = 0; i < 3; i++) {
if(mempll[i].delay >= 32) {
if (mempll[i].delay >= 32) {
die("MEMPLL calibration fail\n");
}
}
@ -704,7 +704,7 @@ void dramc_runtime_config(u32 channel,
/* if frequency >1600, tCKE should >7 clk */
setbits_le32(&ch[channel].ao_regs->dummy, 0x1 << 4);
if(sdram_params->dram_freq * 2 < 1600 * MHz)
if (sdram_params->dram_freq * 2 < 1600 * MHz)
die("set tCKE error in runtime config");
/* DDRPHY C/A and DQ M_CK clock gating enable */

2
src/soc/mediatek/mt8173/dramc_pi_calibration_api.c
View File

@ -79,7 +79,7 @@ void ca_training(u32 channel, const struct mt8173_sdram_params *sdram_params)
0, 1, 3, 3, 3, 4, 4, 5, 5
};
for(i = 0; i < CATRAINING_NUM; i++) {
for (i = 0; i < CATRAINING_NUM; i++) {
ca_shift[i] = params->ca_train[channel][i];
ca_shift_avg8 += ca_shift[i];
}

2
src/soc/mediatek/mt8173/emi.c
View File

@ -89,7 +89,7 @@ static void do_calib(const struct mt8173_sdram_params *sdram_params)
transfer_to_reg_control();
/* do dram calibration for channel A and B */
for(channel = 0; channel < CHANNEL_NUM; channel++) {
for (channel = 0; channel < CHANNEL_NUM; channel++) {
ca_training(channel, sdram_params);
write_leveling(channel, sdram_params);

4
src/soc/nvidia/tegra124/dp.c
View File

@ -891,7 +891,7 @@ static int tegra_dp_link_config(struct tegra_dc_dp_data *dp,
}
/* Set power state if it is not in normal level */
if(tegra_dc_dp_dpcd_read(dp, NV_DPCD_SET_POWER, &dpcd_data))
if (tegra_dc_dp_dpcd_read(dp, NV_DPCD_SET_POWER, &dpcd_data))
return DP_LT_FAILED;
if (dpcd_data == NV_DPCD_SET_POWER_VAL_D3_PWRDWN) {
@ -910,7 +910,7 @@ static int tegra_dp_link_config(struct tegra_dc_dp_data *dp,
/* Enable ASSR if possible */
if (link_cfg->alt_scramber_reset_cap)
if(tegra_dc_dp_set_assr(dp, 1))
if (tegra_dc_dp_set_assr(dp, 1))
return DP_LT_FAILED;
if (tegra_dp_set_link_bandwidth(dp, link_cfg->link_bw)) {

2
src/soc/qualcomm/ipq806x/clock.c
View File

@ -14,7 +14,7 @@ void uart_pll_vote_clk_enable(unsigned int clk_dummy)
setbits_le32(BB_PLL_ENA_SC0_REG, BIT(8));
if (!clk_dummy)
while((read32(PLL_LOCK_DET_STATUS_REG) & BIT(8)) == 0);
while ((read32(PLL_LOCK_DET_STATUS_REG) & BIT(8)) == 0);
}
/**