GNUBoot
/
coreboot-kgpe-d16
2
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

Convert all ck804-based boards to tiny bootblock. 

Signed-off-by: Jonathan Kollasch <jakllsch@kollasch.net>
Acked-by: Patrick Georgi <patrick.georgi@coresystems.de>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5991 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
This commit is contained in:
Jonathan Kollasch 2010-10-26 16:10:20 +00:00 committed by Jonathan A. Kollasch
parent 9d4212fff2
commit 4a8d9938b2
8 changed files with 33 additions and 24 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

4
src/mainboard/asus/a8n_e/romstage.c
View File

@ -79,7 +79,6 @@ static inline int spd_read_byte(unsigned device, unsigned address)
#include "cpu/amd/car/post_cache_as_ram.c"
#include "cpu/amd/model_fxx/init_cpus.c"
#include "southbridge/nvidia/ck804/ck804_enable_rom.c"
#include "northbridge/amd/amdk8/early_ht.c"
static void sio_setup(void)
@ -119,9 +118,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
enumerate_ht_chain();
sio_setup();
/* Setup the ck804 */
ck804_enable_rom();
}
if (bist == 0)

4
src/mainboard/msi/ms7135/romstage.c
View File

@ -85,7 +85,6 @@ static inline int spd_read_byte(unsigned device, unsigned address)
#include "cpu/amd/car/post_cache_as_ram.c"
#include "cpu/amd/model_fxx/init_cpus.c"
#include "southbridge/nvidia/ck804/ck804_enable_rom.c"
#include "northbridge/amd/amdk8/early_ht.c"
static void sio_setup(void)
@ -126,9 +125,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
enumerate_ht_chain();
sio_setup();
/* Setup the ck804 */
ck804_enable_rom();
}
if (bist == 0) {

4
src/mainboard/sunw/ultra40/romstage.c
View File

@ -97,7 +97,6 @@ static inline int spd_read_byte(unsigned device, unsigned address)
#include "cpu/amd/model_fxx/init_cpus.c"
#include "southbridge/nvidia/ck804/ck804_enable_rom.c"
#include "northbridge/amd/amdk8/early_ht.c"
static void sio_setup(void)
@ -147,9 +146,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
enumerate_ht_chain();
sio_setup();
/* Setup the ck804 */
ck804_enable_rom();
}
if (bist == 0) {

4
src/mainboard/tyan/s2891/romstage.c
View File

@ -69,7 +69,6 @@ static inline int spd_read_byte(unsigned device, unsigned address)
#include "cpu/amd/model_fxx/init_cpus.c"
#include "southbridge/nvidia/ck804/ck804_enable_rom.c"
#include "northbridge/amd/amdk8/early_ht.c"
static void sio_setup(void)
@ -122,9 +121,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
enumerate_ht_chain();
sio_setup();
/* Setup the ck804 */
ck804_enable_rom();
}
if (bist == 0) {

4
src/mainboard/tyan/s2892/romstage.c
View File

@ -75,7 +75,6 @@ static inline int spd_read_byte(unsigned device, unsigned address)
#include "cpu/amd/model_fxx/init_cpus.c"
#include "southbridge/nvidia/ck804/ck804_enable_rom.c"
#include "northbridge/amd/amdk8/early_ht.c"
static void sio_setup(void)
@ -116,9 +115,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
enumerate_ht_chain();
sio_setup();
/* Setup the ck804 */
ck804_enable_rom();
}
if (bist == 0) {

4
src/mainboard/tyan/s2895/romstage.c
View File

@ -89,7 +89,6 @@ static inline int spd_read_byte(unsigned device, unsigned address)
#include "cpu/amd/model_fxx/init_cpus.c"
#include "southbridge/nvidia/ck804/ck804_enable_rom.c"
#include "northbridge/amd/amdk8/early_ht.c"
static void sio_setup(void)
@ -140,9 +139,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
enumerate_ht_chain();
sio_setup();
/* Setup the ck804 */
ck804_enable_rom();
}
if (bist == 0) {

5
src/southbridge/nvidia/ck804/Kconfig
View File

@ -3,6 +3,11 @@ config SOUTHBRIDGE_NVIDIA_CK804
select HAVE_HARD_RESET
select HAVE_USBDEBUG
select IOAPIC
select TINY_BOOTBLOCK
config BOOTBLOCK_SOUTHBRIDGE_INIT
string
default "southbridge/nvidia/ck804/bootblock.c" if SOUTHBRIDGE_NVIDIA_CK804
config ID_SECTION_OFFSET
hex

28
src/southbridge/nvidia/ck804/bootblock.c Normal file
View File

@ -0,0 +1,28 @@
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2010 Jonathan Kollasch <jakllsch@kollasch.net>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
#include <arch/io.h>
#include <arch/romcc_io.h>
#include "southbridge/nvidia/ck804/ck804_enable_rom.c"
static void bootblock_southbridge_init(void)
{
ck804_enable_rom();
}