mainboard/intel/minnowmax: use Baytrail Gold3 FSP
Baytrail Gold3 FSP support memory down configuration. Update Minnow Max to use Gold3 FSP. Set memory down data in devicetree.cb, instead of use different FSP image. Change-Id: Ic03da2d2a1cee5144b9a013d3dd9f982ff043123 Signed-off-by: York Yang <york.yang@intel.com> Reviewed-on: http://review.coreboot.org/7581 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com> Reviewed-by: Martin Roth <gaumless@gmail.com>
This commit is contained in:
York Yang
Martin Roth
parent
5f19eb6f40
commit
4a91f64431
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@ -2,6 +2,7 @@
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## This file is part of the coreboot project.
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##
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## Copyright (C) 2013-2014 Sage Electronic Engineering, LLC.
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## Copyright (C) 2014 Intel Corporation
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##
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## This program is free software; you can redistribute it and/or modify
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## it under the terms of the GNU General Public License as published by
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@ -57,10 +58,6 @@ config MINNOWMAX_2GB_SKU
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bool "2GB"
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endchoice
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config MMCONF_BASE_ADDRESS
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hex
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default 0xe0000000
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config IRQ_SLOT_COUNT
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int
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default 18
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@ -73,23 +70,18 @@ config CACHE_ROM_SIZE_OVERRIDE
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hex
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default 0x800000
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config FSP_LOC
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hex
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default 0xfffc0000
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config FSP_FILE
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string
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default "../intel/mainboard/intel/minnowmax/fsp/FvFsp_E3825_2gb.bin" if MINNOWMAX_2GB_SKU
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default "../intel/mainboard/intel/minnowmax/fsp/FvFsp_E3825_1gb.bin"
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default "../intel/fsp/baytrail/BAYTRAIL_FSP.fd"
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config MRC_CACHE_LOC_OVERRIDE
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hex
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default 0xfff90000
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default 0xfff80000
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depends on ENABLE_FSP_FAST_BOOT
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config CBFS_SIZE
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hex
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default 0x00300000
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default 0x00200000
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config DRIVERS_PS2_KEYBOARD
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bool
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@ -119,10 +111,6 @@ config POST_DEVICE
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config VGA_BIOS
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bool
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default n
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config VGA_BIOS_FILE
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string
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default "../intel/mainboard/intel/minnowmax/Vga.dat" if VGA_BIOS
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default y if FSP_PACKAGE_DEFAULT
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endif # BOARD_INTEL_MINNOWMAX
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@ -2,6 +2,7 @@
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## This file is part of the coreboot project.
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##
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## Copyright (C) 2013-2014 Sage Electronic Engineering, LLC.
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## Copyright (C) 2014 Intel Corporation
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##
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## This program is free software; you can redistribute it and/or modify
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## it under the terms of the GNU General Public License as published by
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@ -36,6 +37,23 @@ chip soc/intel/fsp_baytrail
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register "PcdLpssSioEnablePciMode" = "LPSS_PCI_MODE_DEFAULT"
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register "AzaliaAutoEnable" = "AZALIA_FOLLOWS_DEVICETREE"
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register "LpeAcpiModeEnable" = "LPE_ACPI_MODE_DISABLED"
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register "IgdRenderStandby" = "IGD_RENDER_STANDBY_ENABLE"
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register "EnableMemoryDown" = "MEMORY_DOWN_ENABLE"
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register "DRAMSpeed" = "DRAM_SPEED_1066MHZ"
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register "DRAMType" = "DRAM_TYPE_DDR3L"
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register "DIMM0Enable" = "DIMM0_ENABLE"
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register "DIMM1Enable" = "DIMM1_DISABLE"
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register "DIMMDWidth" = "DIMM_DWIDTH_X16"
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register "DIMMDensity" = "DIMM_DENSITY_2G_BIT"
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register "DIMMBusWidth" = "DIMM_BUS_WIDTH_64BIT"
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register "DIMMSides" = "DIMM_SIDES_1RANK"
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register "DIMMtCL" = "11"
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register "DIMMtRPtRCD" = "11"
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register "DIMMtWR" = "12"
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register "DIMMtWTR" = "6"
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register "DIMMtRRD" = "6"
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register "DIMMtRTP" = "6"
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register "DIMMtFAW" = "20"
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device cpu_cluster 0 on
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device lapic 0 on end
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@ -3,6 +3,7 @@
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*
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* Copyright (C) 2013 Google Inc.
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* Copyright (C) 2013 Sage Electronic Engineering, LLC.
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* Copyright (C) 2014 Intel Corporation
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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@ -20,6 +21,7 @@
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#include <baytrail/romstage.h>
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#include <drivers/intel/fsp/fsp_util.h>
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#include "chip.h"
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/**
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* /brief mainboard call for setup that needs to be done before fsp init
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@ -53,8 +55,15 @@ void romstage_fsp_rt_buffer_callback(FSP_INIT_RT_BUFFER *FspRtBuffer)
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{
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UPD_DATA_REGION *UpdData = FspRtBuffer->Common.UpdDataRgnPtr;
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/* Disable 2nd DIMM */
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UpdData->PcdMrcInitSPDAddr2 = 0x00;
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/*
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* Minnow Max Board : 1GB SKU uses 2Gb density memory
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* 2GB SKU uses 4Gb densiry memory
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*
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* devicetree.cb assume 1GB SKU board
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*/
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if (CONFIG_MINNOWMAX_2GB_SKU)
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UpdData->PcdMemoryParameters.DIMMDensity
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+= (DIMM_DENSITY_4G_BIT - DIMM_DENSITY_2G_BIT);
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return;
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}
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