diff --git a/src/northbridge/intel/x4x/gma.c b/src/northbridge/intel/x4x/gma.c
index d2d2bb067d..68d382ef20 100644
--- a/src/northbridge/intel/x4x/gma.c
+++ b/src/northbridge/intel/x4x/gma.c
@@ -48,11 +48,9 @@ static void gma_func0_init(struct device *dev)
 static void gma_func0_disable(struct device *dev)
 {
 	struct device *dev_host = pcidev_on_root(0, 0);
-	u16 ggc;
 
-	ggc = pci_read_config16(dev_host, D0F0_GGC);
-	ggc |= (1 << 1); /* VGA cycles to discrete GPU */
-	pci_write_config16(dev_host, D0F0_GGC, ggc);
+	/* VGA cycles to discrete GPU */
+	pci_or_config16(dev_host, D0F0_GGC, 1 << 1);
 }
 
 static void gma_generate_ssdt(const struct device *device)
diff --git a/src/northbridge/intel/x4x/raminit.c b/src/northbridge/intel/x4x/raminit.c
index e505a5bcdd..5fc9a7ac39 100644
--- a/src/northbridge/intel/x4x/raminit.c
+++ b/src/northbridge/intel/x4x/raminit.c
@@ -597,10 +597,9 @@ static void checkreset_ddr2(int boot_path)
 		pci_write_config8(PCI_DEV(0, 0x1f, 0), 0xa2, pmcon2);
 
 		/* do magic 0xf0 thing. */
-		u8 reg8 = pci_read_config8(PCI_DEV(0, 0, 0), 0xf0);
-		pci_write_config8(PCI_DEV(0, 0, 0), 0xf0, reg8 & ~(1 << 2));
-		reg8 = pci_read_config8(PCI_DEV(0, 0, 0), 0xf0);
-		pci_write_config8(PCI_DEV(0, 0, 0), 0xf0, reg8 |  (1 << 2));
+		pci_and_config8(PCI_DEV(0, 0, 0), 0xf0, ~(1 << 2));
+
+		pci_or_config8(PCI_DEV(0, 0, 0), 0xf0, (1 << 2));
 
 		full_reset();
 	}
@@ -690,11 +689,10 @@ void sdram_initialize(int boot_path, const u8 *spd_map)
 
 	do_raminit(&s, fast_boot);
 
-	reg8 = pci_read_config8(PCI_DEV(0, 0x1f, 0), 0xa2);
-	pci_write_config8(PCI_DEV(0, 0x1f, 0), 0xa2, reg8 & ~0x80);
+	pci_and_config8(PCI_DEV(0, 0x1f, 0), 0xa2, (u8)~0x80);
+
+	pci_or_config8(PCI_DEV(0, 0, 0), 0xf4, 1);
 
-	reg8 = pci_read_config8(PCI_DEV(0, 0, 0), 0xf4);
-	pci_write_config8(PCI_DEV(0, 0, 0), 0xf4, reg8 | 1);
 	printk(BIOS_DEBUG, "RAM initialization finished.\n");
 
 	cbmem_was_inited = !cbmem_recovery(s.boot_path == BOOT_PATH_RESUME);
diff --git a/src/northbridge/intel/x4x/raminit_ddr23.c b/src/northbridge/intel/x4x/raminit_ddr23.c
index ef1094f92c..332af327f5 100644
--- a/src/northbridge/intel/x4x/raminit_ddr23.c
+++ b/src/northbridge/intel/x4x/raminit_ddr23.c
@@ -1701,7 +1701,6 @@ static void configure_mmap(struct sysinfo *s)
 	u16 ggc2uma[] = { 0, 1, 4, 8, 16, 32, 48, 64, 128, 256, 96,
 			  160, 224, 352 };
 	u8 ggc2gtt[] = { 0, 1, 0, 2, 0, 0, 0, 0, 0, 2, 3, 4};
-	u8 reg8;
 
 	ggc = pci_read_config16(PCI_DEV(0, 0, 0), 0x52);
 	gfxsize = ggc2uma[(ggc & 0xf0) >> 4];
@@ -1745,11 +1744,8 @@ static void configure_mmap(struct sysinfo *s)
 	pci_write_config16(PCI_DEV(0, 0, 0), 0xa2, touud);
 	pci_write_config32(PCI_DEV(0, 0, 0), 0xa4, gfxbase << 20);
 	pci_write_config32(PCI_DEV(0, 0, 0), 0xa8, gttbase << 20);
-	/* Enable and set tseg size to 2M */
-	reg8 = pci_read_config8(PCI_DEV(0, 0, 0), D0F0_ESMRAMC);
-	reg8 &= ~0x7;
-	reg8 |= (1 << 1) | (1 << 0); /* 2M and TSEG_Enable */
-	pci_write_config8(PCI_DEV(0, 0, 0), D0F0_ESMRAMC, reg8);
+	/* Enable and set TSEG size to 2M */
+	pci_update_config8(PCI_DEV(0, 0, 0), D0F0_ESMRAMC, ~0x07, (1 << 1) | (1 << 0));
 	pci_write_config32(PCI_DEV(0, 0, 0), 0xac, tsegbase << 20);
 }