arm64: Make exceptions use the transition library
Transition library acts as a common interface for handling exceptions. The only thing that needs to be implemented by exception.c is the exc_dispatch routine to handle the exceptions as required. BUG=chrome-os-partner:30785 BRANCH=None TEST=Compiles successfully and exceptions are tested using test_exc Change-Id: I90b4861909189adfe8449b9d4590965e6b743c00 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: b83c9404407dd4dd2dda4e4eaed0b443f0f58425 Original-Change-Id: Ibb643d7ea2f9aabbc66439549ea2168fd66ced5e Original-Signed-off-by: Furquan Shaikh <furquan@google.com> Original-Reviewed-on: https://chromium-review.googlesource.com/217143 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Tested-by: Furquan Shaikh <furquan@chromium.org> Original-Commit-Queue: Furquan Shaikh <furquan@chromium.org> Reviewed-on: http://review.coreboot.org/9071 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
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@ -38,7 +38,6 @@ bootblock-$(CONFIG_ARM_BOOTBLOCK_NORMAL) += bootblock_normal.c
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bootblock-y += cache.c
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bootblock-y += cpu.S
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bootblock-$(CONFIG_BOOTBLOCK_CONSOLE) += exception.c
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bootblock-$(CONFIG_BOOTBLOCK_CONSOLE) += exception_asm.S
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bootblock-c-ccopts += $(armv8_flags)
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bootblock-S-ccopts += $(armv8_asm_flags)
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@ -53,7 +52,6 @@ ifeq ($(CONFIG_ARCH_ROMSTAGE_ARMV8_64),y)
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romstage-y += cache.c
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romstage-y += cpu.S
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romstage-y += exception.c
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romstage-y += exception_asm.S
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romstage-c-ccopts += $(armv8_flags)
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romstage-S-ccopts += $(armv8_asm_flags)
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@ -71,7 +69,6 @@ ifeq ($(CONFIG_ARCH_RAMSTAGE_ARMV8_64),y)
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ramstage-y += cache.c
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ramstage-y += cpu.S
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ramstage-y += exception.c
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ramstage-y += exception_asm.S
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ramstage-y += mmu.c
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ramstage-c-ccopts += $(armv8_flags)
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@ -31,6 +31,7 @@
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#include <types.h>
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#include <arch/cache.h>
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#include <arch/exception.h>
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#include <arch/transition.h>
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#include <console/console.h>
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#include <arch/lib_helpers.h>
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@ -80,24 +81,28 @@ static struct exception_handler_info exceptions[EXC_COUNT] = {
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[EXC_SERROR_ELX_32] = {"_serror_elx_32"},
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};
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static void print_regs(struct exception_state *state)
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static void print_regs(struct exc_state *exc_state)
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{
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int i;
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uint64_t far_el3;
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struct elx_state *elx = &exc_state->elx;
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struct regs *regs = &exc_state->regs;
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far_el3 = raw_read_far_el3();
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uint64_t elx_esr = raw_read_esr_current();
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uint64_t elx_far = raw_read_far_current();
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printk(BIOS_DEBUG, "ELR = 0x%016llx\n", state->elr);
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printk(BIOS_DEBUG, "ESR = 0x%08llx\n", state->esr);
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printk(BIOS_DEBUG, "FAR_EL3 = 0x%016llx\n", far_el3);
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for (i = 0; i < 31; i++)
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printk(BIOS_DEBUG, "X%02d = 0x%016llx\n", i, state->regs[i]);
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printk(BIOS_DEBUG, "ELR = 0x%016llx\n", elx->elr);
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printk(BIOS_DEBUG, "ESR = 0x%016llx\n", elx_esr);
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printk(BIOS_DEBUG, "SPSR = 0x%08llx\n", elx->spsr);
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printk(BIOS_DEBUG, "FAR = 0x%016llx\n", elx_far);
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for (i = X0_INDEX; i < XMAX_INDEX; i++)
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printk(BIOS_DEBUG, "X%02d = 0x%016llx\n", i, regs->x[i]);
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}
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void exception_dispatch(struct exception_state *state, int idx)
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void exc_dispatch(struct exc_state *exc_state, uint64_t idx)
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{
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if (idx >= EXC_COUNT) {
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printk(BIOS_DEBUG, "Bad exception index %d.\n", idx);
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printk(BIOS_DEBUG, "Bad exception index %lx.\n",
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(unsigned long)idx);
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} else {
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struct exception_handler_info *info = &exceptions[idx];
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@ -106,14 +111,17 @@ void exception_dispatch(struct exception_state *state, int idx)
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else
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printk(BIOS_DEBUG, "exception _not_used.\n");
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}
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print_regs(state);
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print_regs(exc_state);
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if (test_exc) {
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state->elr += 4;
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exc_state->elx.elr += 4;
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raw_write_elr_current(exc_state->elx.elr);
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test_exc = 0;
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printk(BIOS_DEBUG, "new ELR = 0x%016llx\n", state->elr);
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printk(BIOS_DEBUG, "new ELR = 0x%016llx\n", exc_state->elx.elr);
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} else
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die("exception");
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exc_exit(&exc_state->regs);
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}
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static uint64_t test_exception(void)
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@ -129,8 +137,7 @@ static uint64_t test_exception(void)
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void exception_hwinit(void)
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{
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extern void *exception_table;
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set_vbar(&exception_table);
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exc_set_vbar();
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}
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void exception_init(void)
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@ -1,126 +0,0 @@
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/*
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* This file is part of the libpayload project.
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*
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* Copyright 2014 Google Inc.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. The name of the author may not be used to endorse or promote products
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* derived from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*/
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#include <arch/asm.h>
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.macro eentry lbl id
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.align 7
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\lbl:
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stp x30, xzr, [sp, #-16]!
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bl exception_prologue
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mov x1, \id
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bl exception_handler
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.endm
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.align 11
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.global exception_table
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exception_table:
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eentry sync_el3_sp0,#0
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eentry irq_el3_sp0,#1
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eentry fiq_el3_sp0,#2
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eentry serror_el3_sp0,#3
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eentry sync_el3_sp3,#4
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eentry irq_el3_sp3,#5
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eentry fiq_el3_sp3,#6
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eentry serror_el3_sp3,#7
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eentry sync_elx_64,#8
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eentry irq_elx_64,#9
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eentry fiq_elx_64,#10
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eentry serror_elx_64,#11
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eentry sync_elx_32,#12
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eentry irq_elx_32,#13
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eentry fiq_elx_32,#14
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eentry serror_elx_32,#15
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exception_prologue:
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/* Save all registers x0-x29 */
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stp x28, x29, [sp, #-16]!
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stp x26, x27, [sp, #-16]!
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stp x24, x25, [sp, #-16]!
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stp x22, x23, [sp, #-16]!
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stp x20, x21, [sp, #-16]!
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stp x18, x19, [sp, #-16]!
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stp x16, x17, [sp, #-16]!
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stp x14, x15, [sp, #-16]!
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stp x12, x13, [sp, #-16]!
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stp x10, x11, [sp, #-16]!
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stp x8, x9, [sp, #-16]!
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stp x6, x7, [sp, #-16]!
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stp x4, x5, [sp, #-16]!
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stp x2, x3, [sp, #-16]!
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stp x0, x1, [sp, #-16]!
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/* Save the exception reason on stack */
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mrs x1, esr_el3
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/* Save the return address on stack */
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mrs x0, elr_el3
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stp x0, x1, [sp, #-16]!
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ret
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exception_handler:
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/* Save address of saved registers into x0
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* This acts as first argument to exception_dispatch
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*/
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mov x0, sp
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bl exception_dispatch
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/* Pop return address and exception reason saved on stack */
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ldp x0, x1, [sp], #16
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msr elr_el3, x0
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msr esr_el3, x1
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/* Pop registers x0-x30 */
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ldp x0, x1, [sp], #16
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ldp x2, x3, [sp], #16
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ldp x4, x5, [sp], #16
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ldp x6, x7, [sp], #16
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ldp x8, x9, [sp], #16
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ldp x10, x11, [sp], #16
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ldp x12, x13, [sp], #16
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ldp x14, x15, [sp], #16
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ldp x16, x17, [sp], #16
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ldp x18, x19, [sp], #16
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ldp x20, x21, [sp], #16
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ldp x22, x23, [sp], #16
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ldp x24, x25, [sp], #16
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ldp x26, x27, [sp], #16
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ldp x28, x29, [sp], #16
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ldp x30, xzr, [sp], #16
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eret
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.global set_vbar
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set_vbar:
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/* Initialize the exception table address in vbar for EL3 */
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msr vbar_el3, x0
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dsb sy
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isb
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ret
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@ -30,19 +30,8 @@
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#ifndef _ARCH_EXCEPTION_H
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#define _ARCH_EXCEPTION_H
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#include <stdint.h>
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struct exception_state
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{
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uint64_t elr;
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uint64_t esr;
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uint64_t regs[31];
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} __attribute__((packed));
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/* Initialize the exception handling on the current CPU. */
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void exception_hwinit(void);
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void exception_init(void);
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void set_vbar(void *vbar);
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void exception_dispatch(struct exception_state *state, int idx);
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#endif
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