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mb/intel/mtlrvp: Enable WWAN ACPI 

This patch enables FM350GL 5G WWAN support for mtlrvp.

BUG=b:224325352
BRANCH=None
TEST=Build and boot mtlrvp to ChromeOS. Ensure that WWAN module 00:1c.6
is enumerated as part of lspci and cbmem -c in AP console. Also verify
generation of PXSX Device as part of SSDT. Able to connect WiFi and
access internet.

cbmem -c:
\_SB.PCI0.RP07: Enable RTD3 for PCI: 00:1c.6 (Intel PCIe Runtime D3)
\_SB.PCI0.RP07: Enable WWAN for PCI: 00:1c.6 (Fibocom FM-350-GL)

SSDT:
Scope (\_SB.PCI0.RP07)
{
 Device (PXSX)

Signed-off-by: Harsha B R <harsha.b.r@intel.com>
Change-Id: I870cc0782fb989f1bdbe369a4a12630a62729d8e
Signed-off-by: Jamie Ryu <jamie.m.ryu@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/72779
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Krishna P Bhat D <krishna.p.bhat.d@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
This commit is contained in:
Harsha B R 2023-02-04 11:09:24 +05:30 committed by Sridhar Siricilla
parent b2d5e466d5
commit 4aa7d2d5ac
2 changed files with 18 additions and 0 deletions
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1
src/mainboard/intel/mtlrvp/Kconfig
View File

@ -28,6 +28,7 @@ config CHROMEOS
config BOARD_SPECIFIC_OPTIONS
def_bool y
select INTEL_LPSS_UART_FOR_CONSOLE
select DRIVERS_WWAN_FM350GL
config MAINBOARD_DIR
default "intel/mtlrvp"

17
src/mainboard/intel/mtlrvp/variants/baseboard/mtlrvp_p/devicetree.cb
View File

@ -101,6 +101,23 @@ chip soc/intel/meteorlake
.clk_req = 1,
.flags = PCIE_RP_CLK_REQ_DETECT | PCIE_RP_LTR,
}"
chip soc/intel/common/block/pcie/rtd3
register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_C05)"
register "reset_off_delay_ms" = "20"
register "srcclk_pin" = "1"
register "ext_pm_support" = "ACPI_PCIE_RP_EMIT_ALL"
register "skip_on_off_support" = "true"
device generic 0 alias rp7_rtd3 on end
end
chip drivers/wwan/fm
register "fcpo_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_E07)"
register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_A15)"
register "perst_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_C05)"
register "wake_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_F10)"
register "add_acpi_dma_property" = "true"
use rp7_rtd3 as rtd3dev
device generic 0 on end
end
end # WWAN
device ref pcie_rp8 on
# Enable PCH PCIE RP 8 using CLK 5