ACPI: Separate device_nvs_t

Remove typedef device_nvs_t and move struct device_nvs
outside of global_nvs. Also remove padding and the reserve
for chromeos_acpi_t.

Change-Id: I878746b1f0f9152a27dc58e373d58115e2dff22c
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49476
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>

src/acpi/Kconfig

@@ -30,6 +30,9 @@ config ACPI_SOC_NVS
 	  Set to indicate <soc/nvs.h> exists for the platform with a definition
 	  for global_nvs.
 
+config ACPI_HAS_DEVICE_NVS
+	bool
+
 config ACPI_NO_PCAT_8259
 	bool
 	help

src/acpi/gnvs.c

@@ -39,7 +39,7 @@ void acpi_create_gnvs(void)
 	gnvs_size = sizeof(struct global_nvs);
 	if (gnvs_size < 0x100)
 		gnvs_size = 0x100;
-	if (gnvs_size > 0x1000)
+	if (CONFIG(ACPI_HAS_DEVICE_NVS))
 		gnvs_size = 0x2000;
 	else if (CONFIG(MAINBOARD_HAS_CHROMEOS))
 		gnvs_size = 0x1000;
@@ -57,6 +57,11 @@ void acpi_create_gnvs(void)
 		gnvs_assign_chromeos((u8 *)gnvs + GNVS_CHROMEOS_ACPI_OFFSET);
 }
 
+void *acpi_get_device_nvs(void)
+{
+	return (u8 *)gnvs + GNVS_DEVICE_NVS_OFFSET;
+}
+
 void acpi_fill_gnvs(void)
 {
 	if (!gnvs)
@@ -68,4 +73,10 @@ void acpi_fill_gnvs(void)
 	acpigen_write_scope("\\");
 	acpigen_write_name_dword("NVSA", (uintptr_t)gnvs);
 	acpigen_pop_len();
+
+	if (CONFIG(ACPI_HAS_DEVICE_NVS)) {
+		acpigen_write_scope("\\");
+		acpigen_write_name_dword("NVSD", (uintptr_t)gnvs + GNVS_DEVICE_NVS_OFFSET);
+		acpigen_pop_len();
+	}
 }

src/include/acpi/acpi_gnvs.h

@@ -8,6 +8,7 @@
 void acpi_create_gnvs(void);
 #if CONFIG(ACPI_SOC_NVS)
 void *acpi_get_gnvs(void);
+void *acpi_get_device_nvs(void);
 #else
 static inline void *acpi_get_gnvs(void) { return NULL; }
 #endif

src/mainboard/facebook/fbg1701/acpi_tables.c

@@ -5,6 +5,7 @@
 #include <arch/ioapic.h>
 #include <soc/acpi.h>
 #include <soc/nvs.h>
+#include <soc/device_nvs.h>
 
 void mainboard_fill_gnvs(struct global_nvs *gnvs)
 {
@@ -20,7 +21,8 @@ void mainboard_fill_gnvs(struct global_nvs *gnvs)
 	gnvs->dpte = 0;
 
 	/* PMIC is configured in I2C1, hide it for the OS */
-	gnvs->dev.lpss_en[LPSS_NVS_I2C2] = 0;
+	struct device_nvs *dev_nvs = acpi_get_device_nvs();
+	dev_nvs->lpss_en[LPSS_NVS_I2C2] = 0;
 }
 
 unsigned long acpi_fill_madt(unsigned long current)

src/mainboard/google/cyan/acpi_tables.c

@@ -6,6 +6,7 @@
 #include <boardid.h>
 #include <soc/acpi.h>
 #include <soc/nvs.h>
+#include <soc/device_nvs.h>
 
 void mainboard_fill_gnvs(struct global_nvs *gnvs)
 {
@@ -21,8 +22,9 @@ void mainboard_fill_gnvs(struct global_nvs *gnvs)
 	gnvs->dpte = 1;
 
 	/* Disable PMIC I2C port for ACPI for all boards except cyan */
+	struct device_nvs *dev_nvs = acpi_get_device_nvs();
 	if (!CONFIG(BOARD_GOOGLE_CYAN))
-		gnvs->dev.lpss_en[LPSS_NVS_I2C2] = 0;
+		dev_nvs->lpss_en[LPSS_NVS_I2C2] = 0;
 
 	gnvs->bdid = board_id();
 }

src/mainboard/google/jecht/dsdt.asl

@@ -18,6 +18,7 @@ DefinitionBlock(
 
 	// global NVS and variables
 	#include <soc/intel/broadwell/pch/acpi/globalnvs.asl>
+	#include <soc/intel/broadwell/acpi/device_nvs.asl>
 
 	// CPU
 	#include <cpu/intel/common/acpi/cpu.asl>

src/mainboard/intel/strago/acpi_tables.c

@@ -7,6 +7,7 @@
 #include <soc/acpi.h>
 #include <soc/iomap.h>
 #include <soc/nvs.h>
+#include <soc/device_nvs.h>
 #include <boardid.h>
 #include "onboard.h"
 
@@ -24,7 +25,8 @@ void mainboard_fill_gnvs(struct global_nvs *gnvs)
 	gnvs->dpte = 1;
 
 	/* PMIC is configured in I2C1, hidden it from OS */
-	gnvs->dev.lpss_en[LPSS_NVS_I2C2] = 0;
+	struct device_nvs *dev_nvs = acpi_get_device_nvs();
+	dev_nvs->lpss_en[LPSS_NVS_I2C2] = 0;
 }
 
 unsigned long acpi_fill_madt(unsigned long current)

src/mainboard/intel/wtm2/dsdt.asl

@@ -18,6 +18,7 @@ DefinitionBlock(
 
 	// global NVS and variables
 	#include <soc/intel/broadwell/pch/acpi/globalnvs.asl>
+	#include <soc/intel/broadwell/acpi/device_nvs.asl>
 
 	// CPU
 	#include <cpu/intel/common/acpi/cpu.asl>

src/mainboard/portwell/m107/acpi_tables.c

@@ -5,6 +5,7 @@
 #include <arch/ioapic.h>
 #include <soc/acpi.h>
 #include <soc/nvs.h>
+#include <soc/device_nvs.h>
 
 void mainboard_fill_gnvs(struct global_nvs *gnvs)
 {
@@ -20,7 +21,8 @@ void mainboard_fill_gnvs(struct global_nvs *gnvs)
 	gnvs->dpte = 0;
 
 	/* PMIC is configured in I2C1, hide it for the OS */
-	gnvs->dev.lpss_en[LPSS_NVS_I2C2] = 0;
+	struct device_nvs *dev_nvs = acpi_get_device_nvs();
+	dev_nvs->lpss_en[LPSS_NVS_I2C2] = 0;
 }
 
 unsigned long acpi_fill_madt(unsigned long current)

src/soc/intel/baytrail/Kconfig

@@ -8,6 +8,7 @@ if SOC_INTEL_BAYTRAIL
 config CPU_SPECIFIC_OPTIONS
 	def_bool y
 	select ACPI_INTEL_HARDWARE_SLEEP_VALUES
+	select ACPI_HAS_DEVICE_NVS
 	select ARCH_ALL_STAGES_X86_32
 	select BOOT_DEVICE_SPI_FLASH_NO_EARLY_WRITES
 	select BOOT_DEVICE_SUPPORTS_WRITES

src/soc/intel/baytrail/acpi/device_nvs.asl

@@ -1,68 +1,74 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 
-/* Device Enabled in ACPI Mode */
+External (NVSD)
 
-S0EN,	8,	/* SDMA Enable */
+OperationRegion (DNVS, SystemMemory, NVSD, 0x1000)
-S1EN,	8,	/* I2C1 Enable */
+Field (DNVS, ByteAcc, NoLock, Preserve)
-S2EN,	8,	/* I2C2 Enable */
+{
-S3EN,	8,	/* I2C3 Enable */
+	/* Device Enabled in ACPI Mode */
-S4EN,	8,	/* I2C4 Enable */
-S5EN,	8,	/* I2C5 Enable */
-S6EN,	8,	/* I2C6 Enable */
-S7EN,	8,	/* I2C7 Enable */
-S8EN,	8,	/* SDMA2 Enable */
-S9EN,	8,	/* SPI Enable */
-SAEN,	8,	/* PWM1 Enable */
-SBEN,	8,	/* PWM2 Enable */
-SCEN,	8,	/* UART2 Enable */
-SDEN,	8,	/* UART2 Enable */
-C0EN,	8,	/* MMC Enable */
-C1EN,	8,	/* SDIO Enable */
-C2EN,	8,	/* SD Card Enable */
-LPEN,	8,	/* LPE Enable */
 
-/* BAR 0 */
+	S0EN,	8,	/* SDMA Enable */
+	S1EN,	8,	/* I2C1 Enable */
+	S2EN,	8,	/* I2C2 Enable */
+	S3EN,	8,	/* I2C3 Enable */
+	S4EN,	8,	/* I2C4 Enable */
+	S5EN,	8,	/* I2C5 Enable */
+	S6EN,	8,	/* I2C6 Enable */
+	S7EN,	8,	/* I2C7 Enable */
+	S8EN,	8,	/* SDMA2 Enable */
+	S9EN,	8,	/* SPI Enable */
+	SAEN,	8,	/* PWM1 Enable */
+	SBEN,	8,	/* PWM2 Enable */
+	SCEN,	8,	/* UART2 Enable */
+	SDEN,	8,	/* UART2 Enable */
+	C0EN,	8,	/* MMC Enable */
+	C1EN,	8,	/* SDIO Enable */
+	C2EN,	8,	/* SD Card Enable */
+	LPEN,	8,	/* LPE Enable */
 
-S0B0,	32,	/* SDMA BAR0 */
+	/* BAR 0 */
-S1B0,	32,	/* I2C1 BAR0 */
-S2B0,	32,	/* I2C2 BAR0 */
-S3B0,	32,	/* I2C3 BAR0 */
-S4B0,	32,	/* I2C4 BAR0 */
-S5B0,	32,	/* I2C5 BAR0 */
-S6B0,	32,	/* I2C6 BAR0 */
-S7B0,	32,	/* I2C7 BAR0 */
-S8B0,	32,	/* SDMA2 BAR0 */
-S9B0,	32,	/* SPI BAR0 */
-SAB0,	32,	/* PWM1 BAR0 */
-SBB0,	32,	/* PWM2 BAR0 */
-SCB0,	32,	/* UART1 BAR0 */
-SDB0,	32,	/* UART2 BAR0 */
-C0B0,	32,	/* MMC BAR0 */
-C1B0,	32,	/* SDIO BAR0 */
-C2B0,	32,	/* SD Card BAR0 */
-LPB0,	32,	/* LPE BAR0 */
 
-/* BAR 1 */
+	S0B0,	32,	/* SDMA BAR0 */
+	S1B0,	32,	/* I2C1 BAR0 */
+	S2B0,	32,	/* I2C2 BAR0 */
+	S3B0,	32,	/* I2C3 BAR0 */
+	S4B0,	32,	/* I2C4 BAR0 */
+	S5B0,	32,	/* I2C5 BAR0 */
+	S6B0,	32,	/* I2C6 BAR0 */
+	S7B0,	32,	/* I2C7 BAR0 */
+	S8B0,	32,	/* SDMA2 BAR0 */
+	S9B0,	32,	/* SPI BAR0 */
+	SAB0,	32,	/* PWM1 BAR0 */
+	SBB0,	32,	/* PWM2 BAR0 */
+	SCB0,	32,	/* UART1 BAR0 */
+	SDB0,	32,	/* UART2 BAR0 */
+	C0B0,	32,	/* MMC BAR0 */
+	C1B0,	32,	/* SDIO BAR0 */
+	C2B0,	32,	/* SD Card BAR0 */
+	LPB0,	32,	/* LPE BAR0 */
 
-S0B1,	32,	/* SDMA BAR1 */
+	/* BAR 1 */
-S1B1,	32,	/* I2C1 BAR1 */
-S2B1,	32,	/* I2C2 BAR1 */
-S3B1,	32,	/* I2C3 BAR1 */
-S4B1,	32,	/* I2C4 BAR1 */
-S5B1,	32,	/* I2C5 BAR1 */
-S6B1,	32,	/* I2C6 BAR1 */
-S7B1,	32,	/* I2C7 BAR1 */
-S8B1,	32,	/* SDMA2 BAR1 */
-S9B1,	32,	/* SPI BAR1 */
-SAB1,	32,	/* PWM1 BAR1 */
-SBB1,	32,	/* PWM2 BAR1 */
-SCB1,	32,	/* UART1 BAR1 */
-SDB1,	32,	/* UART2 BAR1 */
-C0B1,	32,	/* MMC BAR1 */
-C1B1,	32,	/* SDIO BAR1 */
-C2B1,	32,	/* SD Card BAR1 */
-LPB1,	32,	/* LPE BAR1 */
 
-/* Extra */
+	S0B1,	32,	/* SDMA BAR1 */
+	S1B1,	32,	/* I2C1 BAR1 */
+	S2B1,	32,	/* I2C2 BAR1 */
+	S3B1,	32,	/* I2C3 BAR1 */
+	S4B1,	32,	/* I2C4 BAR1 */
+	S5B1,	32,	/* I2C5 BAR1 */
+	S6B1,	32,	/* I2C6 BAR1 */
+	S7B1,	32,	/* I2C7 BAR1 */
+	S8B1,	32,	/* SDMA2 BAR1 */
+	S9B1,	32,	/* SPI BAR1 */
+	SAB1,	32,	/* PWM1 BAR1 */
+	SBB1,	32,	/* PWM2 BAR1 */
+	SCB1,	32,	/* UART1 BAR1 */
+	SDB1,	32,	/* UART2 BAR1 */
+	C0B1,	32,	/* MMC BAR1 */
+	C1B1,	32,	/* SDIO BAR1 */
+	C2B1,	32,	/* SD Card BAR1 */
+	LPB1,	32,	/* LPE BAR1 */
 
-LPFW,	32,	/* LPE BAR2 Firmware */
+	/* Extra */
+
+	LPFW,	32,	/* LPE BAR2 Firmware */
+}

src/soc/intel/baytrail/acpi/globalnvs.asl

@@ -13,7 +13,7 @@ Name(\PICM, 0)		/* IOAPIC/8259 */
 
 External (NVSA)
 
-OperationRegion (GNVS, SystemMemory, NVSA, 0x2000)
+OperationRegion (GNVS, SystemMemory, NVSA, 0x1000)
 Field (GNVS, ByteAcc, NoLock, Preserve)
 {
 	/* Miscellaneous */
@@ -56,9 +56,6 @@ Field (GNVS, ByteAcc, NoLock, Preserve)
 	/* ChromeOS specific */
 	Offset (0x100),
 	#include <vendorcode/google/chromeos/acpi/gnvs.asl>
-
-	Offset (0x1000),
-	#include <soc/intel/baytrail/acpi/device_nvs.asl>
 }
 
 /* Set flag to enable USB charging in S3 */

src/soc/intel/baytrail/acpi/platform.asl

@@ -1,5 +1,6 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 
+#include <soc/intel/baytrail/acpi/device_nvs.asl>
 #include <southbridge/intel/common/acpi/platform.asl>
 
 /*

src/soc/intel/baytrail/include/soc/device_nvs.h

@@ -24,7 +24,7 @@
 #define SCC_NVS_SDIO		1
 #define SCC_NVS_SD		2
 
-typedef struct {
+struct __packed device_nvs {
 	/* Device Enabled in ACPI Mode */
 	u8	lpss_en[14];
 	u8	scc_en[3];
@@ -42,7 +42,6 @@ typedef struct {
 
 	/* Extra */
 	u32	lpe_fw; /* LPE Firmware */
-	u8	rsvd1[3930]; /* Add padding so sizeof(device_nvs_t) == 0x1000 */
+};
-} __packed device_nvs_t;
 
 #endif

src/soc/intel/baytrail/include/soc/nvs.h

@@ -4,7 +4,6 @@
 #define _BAYTRAIL_NVS_H_
 
 #include <stdint.h>
-#include <soc/device_nvs.h>
 
 struct __packed global_nvs {
 	/* Miscellaneous */
@@ -43,15 +42,6 @@ struct __packed global_nvs {
 	u32	obsolete_cmem; /* 0x30 - CBMEM TOC */
 	u32	tolm; /* 0x34 - Top of Low Memory */
 	u32	cbmc; /* 0x38 - coreboot memconsole */
-	u8	rsvd3[120]; /* 0x3c - 0xb3 - unused */
-
-	u8	unused[76];
-
-	/* ChromeOS specific (0x100-0xfff) */
-	u8	chromeos_reserve[0xf00];
-
-	/* Baytrail LPSS (0x1000) */
-	device_nvs_t dev;
 };
 
 #endif /* _BAYTRAIL_NVS_H_ */

src/soc/intel/baytrail/lpe.c

@@ -12,7 +12,7 @@
 #include <soc/iomap.h>
 #include <soc/iosf.h>
 #include <soc/lpc.h>
-#include <soc/nvs.h>
+#include <soc/device_nvs.h>
 #include <soc/pattrs.h>
 #include <soc/pci_devs.h>
 #include <soc/pm.h>
@@ -52,20 +52,15 @@ static void lpe_enable_acpi_mode(struct device *dev)
 
 		REG_SCRIPT_END
 	};
-	struct global_nvs *gnvs;
+	struct device_nvs *dev_nvs = acpi_get_device_nvs();
-
-	/* Find ACPI NVS to update BARs */
-	gnvs = acpi_get_gnvs();
-	if (!gnvs)
-		return;
 
 	/* Save BAR0, BAR1, and firmware base  to ACPI NVS */
-	assign_device_nvs(dev, &gnvs->dev.lpe_bar0, PCI_BASE_ADDRESS_0);
+	assign_device_nvs(dev, &dev_nvs->lpe_bar0, PCI_BASE_ADDRESS_0);
-	assign_device_nvs(dev, &gnvs->dev.lpe_bar1, PCI_BASE_ADDRESS_1);
+	assign_device_nvs(dev, &dev_nvs->lpe_bar1, PCI_BASE_ADDRESS_1);
-	assign_device_nvs(dev, &gnvs->dev.lpe_fw, FIRMWARE_PCI_REG_BASE);
+	assign_device_nvs(dev, &dev_nvs->lpe_fw, FIRMWARE_PCI_REG_BASE);
 
 	/* Device is enabled in ACPI mode */
-	gnvs->dev.lpe_en = 1;
+	dev_nvs->lpe_en = 1;
 
 	/* Put device in ACPI mode */
 	reg_script_run_on_dev(dev, ops);

src/soc/intel/baytrail/lpss.c

@@ -10,6 +10,7 @@
 
 #include <soc/iosf.h>
 #include <soc/nvs.h>
+#include <soc/device_nvs.h>
 #include <soc/pci_devs.h>
 #include <soc/ramstage.h>
 
@@ -28,24 +29,19 @@ static void dev_enable_acpi_mode(struct device *dev, int iosf_reg, int nvs_index
 		REG_SCRIPT_END
 	};
 	struct resource *bar;
-	struct global_nvs *gnvs;
+	struct device_nvs *dev_nvs = acpi_get_device_nvs();
-
-	/* Find ACPI NVS to update BARs */
-	gnvs = acpi_get_gnvs();
-	if (!gnvs)
-		return;
 
 	/* Save BAR0 and BAR1 to ACPI NVS */
 	bar = find_resource(dev, PCI_BASE_ADDRESS_0);
 	if (bar)
-		gnvs->dev.lpss_bar0[nvs_index] = (u32)bar->base;
+		dev_nvs->lpss_bar0[nvs_index] = (u32)bar->base;
 
 	bar = find_resource(dev, PCI_BASE_ADDRESS_1);
 	if (bar)
-		gnvs->dev.lpss_bar1[nvs_index] = (u32)bar->base;
+		dev_nvs->lpss_bar1[nvs_index] = (u32)bar->base;
 
 	/* Device is enabled in ACPI mode */
-	gnvs->dev.lpss_en[nvs_index] = 1;
+	dev_nvs->lpss_en[nvs_index] = 1;
 
 	/* Put device in ACPI mode */
 	reg_script_run_on_dev(dev, ops);

src/soc/intel/baytrail/scc.c

@@ -7,7 +7,7 @@
 #include <reg_script.h>
 
 #include <soc/iosf.h>
-#include <soc/nvs.h>
+#include <soc/device_nvs.h>
 #include <soc/ramstage.h>
 
 static const struct reg_script scc_start_dll[] = {
@@ -80,24 +80,19 @@ void scc_enable_acpi_mode(struct device *dev, int iosf_reg, int nvs_index)
 		REG_SCRIPT_END
 	};
 	struct resource *bar;
-	struct global_nvs *gnvs;
+	struct device_nvs *dev_nvs = acpi_get_device_nvs();
-
-	/* Find ACPI NVS to update BARs */
-	gnvs = acpi_get_gnvs();
-	if (!gnvs)
-		return;
 
 	/* Save BAR0 and BAR1 to ACPI NVS */
 	bar = find_resource(dev, PCI_BASE_ADDRESS_0);
 	if (bar)
-		gnvs->dev.scc_bar0[nvs_index] = (u32)bar->base;
+		dev_nvs->scc_bar0[nvs_index] = (u32)bar->base;
 
 	bar = find_resource(dev, PCI_BASE_ADDRESS_1);
 	if (bar)
-		gnvs->dev.scc_bar1[nvs_index] = (u32)bar->base;
+		dev_nvs->scc_bar1[nvs_index] = (u32)bar->base;
 
 	/* Device is enabled in ACPI mode */
-	gnvs->dev.scc_en[nvs_index] = 1;
+	dev_nvs->scc_en[nvs_index] = 1;
 
 	/* Put device in ACPI mode */
 	reg_script_run_on_dev(dev, ops);

src/soc/intel/baytrail/smihandler.c

@@ -1,6 +1,7 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 
 #include <stdint.h>
+#include <acpi/acpi_gnvs.h>
 #include <arch/io.h>
 #include <device/pci_ops.h>
 #include <console/console.h>
@@ -17,6 +18,9 @@
 #include <soc/pci_devs.h>
 #include <soc/pm.h>
 #include <soc/nvs.h>
+#include <soc/device_nvs.h>
+
+#include <vendorcode/google/chromeos/gnvs.h>
 
 int southbridge_io_trap_handler(int smif)
 {
@@ -204,6 +208,11 @@ static void southbridge_smi_gsmi(void)
 	*ret = gsmi_exec(sub_command, param);
 }
 
+void *acpi_get_device_nvs(void)
+{
+	return (u8 *)gnvs + GNVS_DEVICE_NVS_OFFSET;
+}
+
 /*
  * soc_legacy: A payload (Depthcharge) has indicated that the
  *   legacy payload (SeaBIOS) is being loaded. Switch devices that are
@@ -212,10 +221,11 @@ static void southbridge_smi_gsmi(void)
  */
 static void soc_legacy(void)
 {
+	struct device_nvs *dev_nvs = acpi_get_device_nvs();
 	u32 reg32;
 
 	/* LPE Device */
-	 if (gnvs->dev.lpe_en) {
+	if (dev_nvs->lpe_en) {
 		reg32 = iosf_port58_read(LPE_PCICFGCTR1);
 		reg32 &=
 		~(LPE_PCICFGCTR1_PCI_CFG_DIS | LPE_PCICFGCTR1_ACPI_INT_EN);
@@ -224,7 +234,7 @@ static void soc_legacy(void)
 
 	/* SCC Devices */
 #define SCC_ACPI_MODE_DISABLE(name_) \
-	do { if (gnvs->dev.scc_en[SCC_NVS_ ## name_]) { \
+	do { if (dev_nvs->scc_en[SCC_NVS_ ## name_]) { \
 		reg32 = iosf_scc_read(SCC_ ## name_ ## _CTL); \
 		reg32 &= ~(SCC_CTL_PCI_CFG_DIS | SCC_CTL_ACPI_INT_EN); \
 		iosf_scc_write(SCC_ ## name_ ## _CTL, reg32); \
@@ -236,7 +246,7 @@ static void soc_legacy(void)
 
 	 /* LPSS Devices */
 #define LPSS_ACPI_MODE_DISABLE(name_) \
-	do { if (gnvs->dev.lpss_en[LPSS_NVS_ ## name_]) { \
+	do { if (dev_nvs->lpss_en[LPSS_NVS_ ## name_]) { \
 		reg32 = iosf_lpss_read(LPSS_ ## name_ ## _CTL); \
 		reg32 &= ~LPSS_CTL_PCI_CFG_DIS | ~LPSS_CTL_ACPI_INT_EN; \
 		iosf_lpss_write(LPSS_ ## name_ ## _CTL, reg32); \

src/soc/intel/braswell/Kconfig

@@ -8,6 +8,7 @@ if SOC_INTEL_BRASWELL
 config CPU_SPECIFIC_OPTIONS
 	def_bool y
 	select ACPI_INTEL_HARDWARE_SLEEP_VALUES
+	select ACPI_HAS_DEVICE_NVS
 	select ARCH_ALL_STAGES_X86_32
 	select BOOT_DEVICE_SPI_FLASH_NO_EARLY_WRITES
 	select BOOT_DEVICE_SUPPORTS_WRITES

src/soc/intel/braswell/acpi/device_nvs.asl

@@ -1,68 +1,74 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 
-/* Device Enabled in ACPI Mode */
+External (NVSD)
 
-S0EN,	8,	/* SDMA Enable */
+OperationRegion (DNVS, SystemMemory, NVSD, 0x1000)
-S1EN,	8,	/* I2C1 Enable */
+Field (DNVS, ByteAcc, NoLock, Preserve)
-S2EN,	8,	/* I2C2 Enable */
+{
-S3EN,	8,	/* I2C3 Enable */
+	/* Device Enabled in ACPI Mode */
-S4EN,	8,	/* I2C4 Enable */
-S5EN,	8,	/* I2C5 Enable */
-S6EN,	8,	/* I2C6 Enable */
-S7EN,	8,	/* I2C7 Enable */
-S8EN,	8,	/* SDMA2 Enable */
-S9EN,	8,	/* SPI Enable */
-SAEN,	8,	/* PWM1 Enable */
-SBEN,	8,	/* PWM2 Enable */
-SCEN,	8,	/* UART2 Enable */
-SDEN,	8,	/* UART2 Enable */
-C0EN,	8,	/* MMC Enable */
-C1EN,	8,	/* SDIO Enable */
-C2EN,	8,	/* SD Card Enable */
-LPEN,	8,	/* LPE Enable */
 
-/* BAR 0 */
+	S0EN,	8,	/* SDMA Enable */
+	S1EN,	8,	/* I2C1 Enable */
+	S2EN,	8,	/* I2C2 Enable */
+	S3EN,	8,	/* I2C3 Enable */
+	S4EN,	8,	/* I2C4 Enable */
+	S5EN,	8,	/* I2C5 Enable */
+	S6EN,	8,	/* I2C6 Enable */
+	S7EN,	8,	/* I2C7 Enable */
+	S8EN,	8,	/* SDMA2 Enable */
+	S9EN,	8,	/* SPI Enable */
+	SAEN,	8,	/* PWM1 Enable */
+	SBEN,	8,	/* PWM2 Enable */
+	SCEN,	8,	/* UART2 Enable */
+	SDEN,	8,	/* UART2 Enable */
+	C0EN,	8,	/* MMC Enable */
+	C1EN,	8,	/* SDIO Enable */
+	C2EN,	8,	/* SD Card Enable */
+	LPEN,	8,	/* LPE Enable */
 
-S0B0,	32,	/* SDMA BAR0 */
+	/* BAR 0 */
-S1B0,	32,	/* I2C1 BAR0 */
-S2B0,	32,	/* I2C2 BAR0 */
-S3B0,	32,	/* I2C3 BAR0 */
-S4B0,	32,	/* I2C4 BAR0 */
-S5B0,	32,	/* I2C5 BAR0 */
-S6B0,	32,	/* I2C6 BAR0 */
-S7B0,	32,	/* I2C7 BAR0 */
-S8B0,	32,	/* SDMA2 BAR0 */
-S9B0,	32,	/* SPI BAR0 */
-SAB0,	32,	/* PWM1 BAR0 */
-SBB0,	32,	/* PWM2 BAR0 */
-SCB0,	32,	/* UART1 BAR0 */
-SDB0,	32,	/* UART2 BAR0 */
-C0B0,	32,	/* MMC BAR0 */
-C1B0,	32,	/* SDIO BAR0 */
-C2B0,	32,	/* SD Card BAR0 */
-LPB0,	32,	/* LPE BAR0 */
 
-/* BAR 1 */
+	S0B0,	32,	/* SDMA BAR0 */
+	S1B0,	32,	/* I2C1 BAR0 */
+	S2B0,	32,	/* I2C2 BAR0 */
+	S3B0,	32,	/* I2C3 BAR0 */
+	S4B0,	32,	/* I2C4 BAR0 */
+	S5B0,	32,	/* I2C5 BAR0 */
+	S6B0,	32,	/* I2C6 BAR0 */
+	S7B0,	32,	/* I2C7 BAR0 */
+	S8B0,	32,	/* SDMA2 BAR0 */
+	S9B0,	32,	/* SPI BAR0 */
+	SAB0,	32,	/* PWM1 BAR0 */
+	SBB0,	32,	/* PWM2 BAR0 */
+	SCB0,	32,	/* UART1 BAR0 */
+	SDB0,	32,	/* UART2 BAR0 */
+	C0B0,	32,	/* MMC BAR0 */
+	C1B0,	32,	/* SDIO BAR0 */
+	C2B0,	32,	/* SD Card BAR0 */
+	LPB0,	32,	/* LPE BAR0 */
 
-S0B1,	32,	/* SDMA BAR1 */
+	/* BAR 1 */
-S1B1,	32,	/* I2C1 BAR1 */
-S2B1,	32,	/* I2C2 BAR1 */
-S3B1,	32,	/* I2C3 BAR1 */
-S4B1,	32,	/* I2C4 BAR1 */
-S5B1,	32,	/* I2C5 BAR1 */
-S6B1,	32,	/* I2C6 BAR1 */
-S7B1,	32,	/* I2C7 BAR1 */
-S8B1,	32,	/* SDMA2 BAR1 */
-S9B1,	32,	/* SPI BAR1 */
-SAB1,	32,	/* PWM1 BAR1 */
-SBB1,	32,	/* PWM2 BAR1 */
-SCB1,	32,	/* UART1 BAR1 */
-SDB1,	32,	/* UART2 BAR1 */
-C0B1,	32,	/* MMC BAR1 */
-C1B1,	32,	/* SDIO BAR1 */
-C2B1,	32,	/* SD Card BAR1 */
-LPB1,	32,	/* LPE BAR1 */
 
-/* Extra */
+	S0B1,	32,	/* SDMA BAR1 */
+	S1B1,	32,	/* I2C1 BAR1 */
+	S2B1,	32,	/* I2C2 BAR1 */
+	S3B1,	32,	/* I2C3 BAR1 */
+	S4B1,	32,	/* I2C4 BAR1 */
+	S5B1,	32,	/* I2C5 BAR1 */
+	S6B1,	32,	/* I2C6 BAR1 */
+	S7B1,	32,	/* I2C7 BAR1 */
+	S8B1,	32,	/* SDMA2 BAR1 */
+	S9B1,	32,	/* SPI BAR1 */
+	SAB1,	32,	/* PWM1 BAR1 */
+	SBB1,	32,	/* PWM2 BAR1 */
+	SCB1,	32,	/* UART1 BAR1 */
+	SDB1,	32,	/* UART2 BAR1 */
+	C0B1,	32,	/* MMC BAR1 */
+	C1B1,	32,	/* SDIO BAR1 */
+	C2B1,	32,	/* SD Card BAR1 */
+	LPB1,	32,	/* LPE BAR1 */
 
-LPFW,	32,	/* LPE BAR2 Firmware */
+	/* Extra */
+
+	LPFW,	32,	/* LPE BAR2 Firmware */
+}

src/soc/intel/braswell/acpi/globalnvs.asl

@@ -13,7 +13,7 @@ Name(\PICM, 0)		/* IOAPIC/8259 */
 
 External (NVSA)
 
-OperationRegion (GNVS, SystemMemory, NVSA, 0x2000)
+OperationRegion (GNVS, SystemMemory, NVSA, 0x1000)
 Field (GNVS, ByteAcc, NoLock, Preserve)
 {
 	/* Miscellaneous */
@@ -58,9 +58,6 @@ Field (GNVS, ByteAcc, NoLock, Preserve)
 	/* ChromeOS specific */
 	Offset (0x100),
 	#include <vendorcode/google/chromeos/acpi/gnvs.asl>
-
-	Offset (0x1000),
-	#include <soc/intel/braswell/acpi/device_nvs.asl>
 }
 
 /* Set flag to enable USB charging in S3 */

src/soc/intel/braswell/acpi/platform.asl

@@ -1,10 +1,11 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 
+#include <soc/intel/braswell/acpi/device_nvs.asl>
+
 /* Enable ACPI _SWS methods */
 #include <soc/intel/common/acpi/acpi_wake_source.asl>
 #include <southbridge/intel/common/acpi/platform.asl>
 
-
 /*
  * The _PTS method (Prepare To Sleep) is called before the OS is
  * entering a sleep state. The sleep state number is passed in Arg0

src/soc/intel/braswell/include/soc/device_nvs.h

@@ -24,7 +24,7 @@
 #define SCC_NVS_SDIO		1
 #define SCC_NVS_SD		2
 
-typedef struct {
+struct __packed device_nvs {
 	/* Device Enabled in ACPI Mode */
 	u8	lpss_en[14];
 	u8	scc_en[3];
@@ -42,6 +42,6 @@ typedef struct {
 
 	/* Extra */
 	u32	lpe_fw; /* LPE Firmware */
-} __packed device_nvs_t;
+};
 
 #endif	/* _SOC_DEVICE_NVS_H_ */

src/soc/intel/braswell/include/soc/nvs.h

@@ -4,7 +4,6 @@
 #define _SOC_NVS_H_
 
 #include <stdint.h>
-#include <soc/device_nvs.h>
 
 struct __packed global_nvs {
 	/* Miscellaneous */
@@ -45,15 +44,6 @@ struct __packed global_nvs {
 	u32	obsolete_cmem; /* 0x30 - CBMEM TOC */
 	u32	tolm; /* 0x34 - Top of Low Memory */
 	u32	cbmc; /* 0x38 - coreboot memconsole */
-	u8	rsvd3[120]; /* 0x3c - 0xb3 - unused */
-
-	u8	unused[76];
-
-	/* ChromeOS specific (0x100-0xfff) */
-	u8	chromeos_reserve[0xf00];
-
-	/* LPSS (0x1000) */
-	device_nvs_t dev;
 };
 
 #endif /* _SOC_NVS_H_ */

src/soc/intel/braswell/lpe.c

@@ -12,7 +12,7 @@
 #include <soc/iomap.h>
 #include <soc/iosf.h>
 #include <soc/lpc.h>
-#include <soc/nvs.h>
+#include <soc/device_nvs.h>
 #include <soc/pattrs.h>
 #include <soc/pci_devs.h>
 #include <soc/pm.h>
@@ -53,20 +53,15 @@ static void lpe_enable_acpi_mode(struct device *dev)
 
 		REG_SCRIPT_END
 	};
-	struct global_nvs *gnvs;
+	struct device_nvs *dev_nvs = acpi_get_device_nvs();
-
-	/* Find ACPI NVS to update BARs */
-	gnvs = acpi_get_gnvs();
-	if (!gnvs)
-		return;
 
 	/* Save BAR0, BAR1, and firmware base  to ACPI NVS */
-	assign_device_nvs(dev, &gnvs->dev.lpe_bar0, PCI_BASE_ADDRESS_0);
+	assign_device_nvs(dev, &dev_nvs->lpe_bar0, PCI_BASE_ADDRESS_0);
-	assign_device_nvs(dev, &gnvs->dev.lpe_bar1, PCI_BASE_ADDRESS_2);
+	assign_device_nvs(dev, &dev_nvs->lpe_bar1, PCI_BASE_ADDRESS_2);
-	assign_device_nvs(dev, &gnvs->dev.lpe_fw, FIRMWARE_PCI_REG_BASE);
+	assign_device_nvs(dev, &dev_nvs->lpe_fw, FIRMWARE_PCI_REG_BASE);
 
 	/* Device is enabled in ACPI mode */
-	gnvs->dev.lpe_en = 1;
+	dev_nvs->lpe_en = 1;
 
 	/* Put device in ACPI mode */
 	reg_script_run_on_dev(dev, ops);

src/soc/intel/braswell/lpss.c

@@ -9,7 +9,7 @@
 #include <reg_script.h>
 
 #include <soc/iosf.h>
-#include <soc/nvs.h>
+#include <soc/device_nvs.h>
 #include <soc/pci_devs.h>
 #include <soc/ramstage.h>
 
@@ -28,24 +28,19 @@ static void dev_enable_acpi_mode(struct device *dev, int iosf_reg, int nvs_index
 		REG_SCRIPT_END
 	};
 	struct resource *bar;
-	struct global_nvs *gnvs;
+	struct device_nvs *dev_nvs = acpi_get_device_nvs();
-
-	/* Find ACPI NVS to update BARs */
-	gnvs = acpi_get_gnvs();
-	if (!gnvs)
-		return;
 
 	/* Save BAR0 and BAR1 to ACPI NVS */
 	bar = find_resource(dev, PCI_BASE_ADDRESS_0);
 	if (bar)
-		gnvs->dev.lpss_bar0[nvs_index] = (u32)bar->base;
+		dev_nvs->lpss_bar0[nvs_index] = (u32)bar->base;
 
 	bar = find_resource(dev, PCI_BASE_ADDRESS_1);
 	if (bar)
-		gnvs->dev.lpss_bar1[nvs_index] = (u32)bar->base;
+		dev_nvs->lpss_bar1[nvs_index] = (u32)bar->base;
 
 	/* Device is enabled in ACPI mode */
-	gnvs->dev.lpss_en[nvs_index] = 1;
+	dev_nvs->lpss_en[nvs_index] = 1;
 
 	/* Put device in ACPI mode */
 	reg_script_run_on_dev(dev, ops);

src/soc/intel/braswell/scc.c

@@ -5,27 +5,22 @@
 #include <device/device.h>
 #include <device/pci.h>
 #include <soc/iosf.h>
-#include <soc/nvs.h>
+#include <soc/device_nvs.h>
 #include <soc/ramstage.h>
 
 void scc_enable_acpi_mode(struct device *dev, int iosf_reg, int nvs_index)
 {
 	struct resource *bar;
-	struct global_nvs *gnvs;
+	struct device_nvs *dev_nvs = acpi_get_device_nvs();
-
-	/* Find ACPI NVS to update BARs */
-	gnvs = acpi_get_gnvs();
-	if (!gnvs)
-		return;
 
 	/* Save BAR0 and BAR1 to ACPI NVS */
 	bar = find_resource(dev, PCI_BASE_ADDRESS_0);
 	if (bar)
-		gnvs->dev.scc_bar0[nvs_index] = bar->base;
+		dev_nvs->scc_bar0[nvs_index] = bar->base;
 	bar = find_resource(dev, PCI_BASE_ADDRESS_2);
 	if (bar)
-		gnvs->dev.scc_bar1[nvs_index] = bar->base;
+		dev_nvs->scc_bar1[nvs_index] = bar->base;
 
 	/* Device is enabled in ACPI mode */
-	gnvs->dev.scc_en[nvs_index] = 1;
+	dev_nvs->scc_en[nvs_index] = 1;
 }

src/soc/intel/broadwell/Kconfig

@@ -11,6 +11,7 @@ config INTEL_LYNXPOINT_LP
 
 config SOC_SPECIFIC_OPTIONS
 	def_bool y
+	select ACPI_HAS_DEVICE_NVS
 	select ACPI_INTEL_HARDWARE_SLEEP_VALUES
 	select BOOT_DEVICE_SUPPORTS_WRITES
 	select CACHE_MRC_SETTINGS

src/soc/intel/broadwell/acpi/device_nvs.asl

@@ -0,0 +1,43 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+External (NVSD)
+
+OperationRegion (DNVS, SystemMemory, NVSD, 0x1000)
+Field (DNVS, ByteAcc, NoLock, Preserve)
+{
+	/* Device enables in ACPI mode */
+
+	S0EN,	8,	// DMA Enable
+	S1EN,	8,	// I2C0 Enable
+	S2EN,	8,	// I2C1 Enable
+	S3EN,	8,	// SPI0 Enable
+	S4EN,	8,	// SPI1 Enable
+	S5EN,	8,	// UART0 Enable
+	S6EN,	8,	// UART1 Enable
+	S7EN,	8,	// SDIO Enable
+	S8EN,	8,	// ADSP Enable
+
+	/* BAR 0 */
+
+	S0B0,	32,	// DMA BAR0
+	S1B0,	32,	// I2C0 BAR0
+	S2B0,	32,	// I2C1 BAR0
+	S3B0,	32,	// SPI0 BAR0
+	S4B0,	32,	// SPI1 BAR0
+	S5B0,	32,	// UART0 BAR0
+	S6B0,	32,	// UART1 BAR0
+	S7B0,	32,	// SDIO BAR0
+	S8B0,	32,	// ADSP BAR0
+
+	/* BAR 1 */
+
+	S0B1,	32,	// DMA BAR1
+	S1B1,	32,	// I2C0 BAR1
+	S2B1,	32,	// I2C1 BAR1
+	S3B1,	32,	// SPI0 BAR1
+	S4B1,	32,	// SPI1 BAR1
+	S5B1,	32,	// UART0 BAR1
+	S6B1,	32,	// UART1 BAR1
+	S7B1,	32,	// SDIO BAR1
+	S8B1,	32,	// ADSP BAR1
+}

src/soc/intel/broadwell/acpi/platform.asl

@@ -1,5 +1,6 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 
+#include <soc/intel/broadwell/acpi/device_nvs.asl>
 #include <southbridge/intel/common/acpi/platform.asl>
 
 /*

src/soc/intel/broadwell/include/soc/device_nvs.h

@@ -15,10 +15,10 @@
 #define SIO_NVS_SDIO		7
 #define SIO_NVS_ADSP		8
 
-typedef struct {
+struct __packed device_nvs {
 	u8	enable[9];
 	u32	bar0[9];
 	u32	bar1[9];
-} __packed device_nvs_t;
+};
 
 #endif

src/soc/intel/broadwell/include/soc/nvs.h

@@ -4,7 +4,6 @@
 #define _BROADWELL_NVS_H_
 
 #include <stdint.h>
-#include <soc/device_nvs.h>
 
 struct __packed global_nvs {
 	/* Miscellaneous */
@@ -35,15 +34,6 @@ struct __packed global_nvs {
 	u32	cbmc; /* 0x1c - 0x1f - coreboot Memory Console */
 	u64	pm1i; /* 0x20 - 0x27 - PM1 wake status bit */
 	u64	gpei; /* 0x28 - 0x2f - GPE wake status bit */
-	u8	unused1[132]; /* 0x30 - 0xb3 - unused */
-
-	u8	unused2[76];
-
-	/* ChromeOS specific (0x100 - 0xfff) */
-	u8	chromeos_reserve[0xf00];
-
-	/* Device specific (0x1000) */
-	device_nvs_t dev;
 };
 
 #endif

src/soc/intel/broadwell/pch/acpi/globalnvs.asl

@@ -12,7 +12,7 @@ Name (\PICM, 0)		// IOAPIC/8259
  */
 
 External (NVSA)
-OperationRegion (GNVS, SystemMemory, NVSA, 0x2000)
+OperationRegion (GNVS, SystemMemory, NVSA, 0x1000)
 Field (GNVS, ByteAcc, NoLock, Preserve)
 {
 	/* Miscellaneous */
@@ -47,40 +47,6 @@ Field (GNVS, ByteAcc, NoLock, Preserve)
 	/* ChromeOS specific */
 	Offset (0x100),
 	#include <vendorcode/google/chromeos/acpi/gnvs.asl>
-
-	Offset (0x1000),
-	/* Device enables in ACPI mode */
-	S0EN,	8,	// DMA Enable
-	S1EN,	8,	// I2C0 Enable
-	S2EN,	8,	// I2C1 Enable
-	S3EN,	8,	// SPI0 Enable
-	S4EN,	8,	// SPI1 Enable
-	S5EN,	8,	// UART0 Enable
-	S6EN,	8,	// UART1 Enable
-	S7EN,	8,	// SDIO Enable
-	S8EN,	8,	// ADSP Enable
-
-	/* BAR 0 */
-	S0B0,	32,	// DMA BAR0
-	S1B0,	32,	// I2C0 BAR0
-	S2B0,	32,	// I2C1 BAR0
-	S3B0,	32,	// SPI0 BAR0
-	S4B0,	32,	// SPI1 BAR0
-	S5B0,	32,	// UART0 BAR0
-	S6B0,	32,	// UART1 BAR0
-	S7B0,	32,	// SDIO BAR0
-	S8B0,	32,	// ADSP BAR0
-
-	/* BAR 1 */
-	S0B1,	32,	// DMA BAR1
-	S1B1,	32,	// I2C0 BAR1
-	S2B1,	32,	// I2C1 BAR1
-	S3B1,	32,	// SPI0 BAR1
-	S4B1,	32,	// SPI1 BAR1
-	S5B1,	32,	// UART0 BAR1
-	S6B1,	32,	// UART1 BAR1
-	S7B1,	32,	// SDIO BAR1
-	S8B1,	32,	// ADSP BAR1
 }
 
 /* Set flag to enable USB charging in S3 */

src/soc/intel/broadwell/pch/adsp.c

@@ -10,7 +10,7 @@
 #include <soc/adsp.h>
 #include <soc/device_nvs.h>
 #include <soc/iobp.h>
-#include <soc/nvs.h>
+#include <soc/device_nvs.h>
 #include <soc/pch.h>
 #include <soc/ramstage.h>
 #include <soc/rcba.h>
@@ -79,20 +79,15 @@ static void adsp_init(struct device *dev)
 	pch_iobp_write(ADSP_IOBP_PMCTL, ADSP_PMCTL_VALUE);
 
 	if (config->sio_acpi_mode) {
-		/* Configure for ACPI mode */
+		struct device_nvs *dev_nvs = acpi_get_device_nvs();
-		struct global_nvs *gnvs;
 
+		/* Configure for ACPI mode */
 		printk(BIOS_INFO, "ADSP: Enable ACPI Mode IRQ3\n");
 
-		/* Find ACPI NVS to update BARs */
-		gnvs = acpi_get_gnvs();
-		if (!gnvs)
-			return;
-
 		/* Save BAR0 and BAR1 to ACPI NVS */
-		gnvs->dev.bar0[SIO_NVS_ADSP] = (u32)bar0->base;
+		dev_nvs->bar0[SIO_NVS_ADSP] = (u32)bar0->base;
-		gnvs->dev.bar1[SIO_NVS_ADSP] = (u32)bar1->base;
+		dev_nvs->bar1[SIO_NVS_ADSP] = (u32)bar1->base;
-		gnvs->dev.enable[SIO_NVS_ADSP] = 1;
+		dev_nvs->enable[SIO_NVS_ADSP] = 1;
 
 		/* Set PCI Config Disable Bit */
 		pch_iobp_update(ADSP_IOBP_PCICFGCTL, ~0, ADSP_PCICFGCTL_PCICD);

src/soc/intel/broadwell/pch/serialio.c

@@ -8,7 +8,7 @@
 #include <device/pci.h>
 #include <device/pci_ids.h>
 #include <soc/iobp.h>
-#include <soc/nvs.h>
+#include <soc/device_nvs.h>
 #include <soc/pci_devs.h>
 #include <soc/pch.h>
 #include <soc/ramstage.h>
@@ -233,20 +233,15 @@ static void serialio_init(struct device *dev)
 	}
 
 	if (config->sio_acpi_mode) {
-		struct global_nvs *gnvs;
+		struct device_nvs *dev_nvs = acpi_get_device_nvs();
-
-		/* Find ACPI NVS to update BARs */
-		gnvs = acpi_get_gnvs();
-		if (!gnvs)
-			return;
 
 		/* Save BAR0 and BAR1 to ACPI NVS */
-		gnvs->dev.bar0[sio_index] = (u32)bar0->base;
+		dev_nvs->bar0[sio_index] = (u32)bar0->base;
-		gnvs->dev.bar1[sio_index] = (u32)bar1->base;
+		dev_nvs->bar1[sio_index] = (u32)bar1->base;
 
 		/* Do not enable UART if it is used as debug port */
 		if (!serialio_uart_is_debug(dev))
-			gnvs->dev.enable[sio_index] = 1;
+			dev_nvs->enable[sio_index] = 1;
 
 		/* Put device in D3hot state via BAR1 */
 		if (dev->path.pci.devfn != PCH_DEVFN_SDMA)