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commonlib/lz4: Avoid unaligned memory access on RISC-V 

From the User-Level ISA Specification v2.0:

   "We do not mandate atomicity for misaligned accesses so simple
    implementations can just use a machine trap and software handler to
    handle misaligned accesses." (— http://riscv.org/specifications/)

Spike traps on unaligned accesses.

Change-Id: Ia57786916f4076cc08513f4e331c2deec9cfa785
Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
Reviewed-on: https://review.coreboot.org/14983
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
This commit is contained in:
Jonathan Neuschäfer 2016-05-27 09:05:02 +02:00 committed by Martin Roth
parent 0a54fb533d
commit 4acb0e7742
1 changed files with 5 additions and 0 deletions
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5
src/commonlib/lz4_wrapper.c
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@ -63,6 +63,11 @@ static void LZ4_copy8(void *dst, const void *src)
: [src]"r"(src), [dst]"r"(dst) : [src]"r"(src), [dst]"r"(dst)
: "memory" ); : "memory" );
#endif #endif
#elif defined(__riscv__)
/* RISC-V implementations may trap on any unaligned access. */
int i;
for (i = 0; i < 8; i++)
((uint8_t *)dst)[i] = ((uint8_t *)src)[i];
#else #else
*(uint64_t *)dst = *(const uint64_t *)src; *(uint64_t *)dst = *(const uint64_t *)src;
#endif #endif