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src/mb: Fix non-local header treated as local 

Also remove some unnedded includes.

Change-Id: I036208a111d009620d8354fa9c97688eb4e872ad
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/27129
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
This commit is contained in:
Elyes HAOUAS 2018-06-16 18:29:33 +02:00 committed by Patrick Georgi
parent eafb31be30
commit 4ad1446b83
60 changed files with 96 additions and 158 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
src/mainboard/advansus/a785e-i/mainboard.c
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@ -21,7 +21,7 @@
#include <cpu/amd/mtrr.h> #include <cpu/amd/mtrr.h>
#include <southbridge/amd/common/amd_defs.h> #include <southbridge/amd/common/amd_defs.h>
#include <device/pci_def.h> #include <device/pci_def.h>
#include "southbridge/amd/rs780/rs780.h" #include <southbridge/amd/rs780/rs780.h>
/* GPIO6. */ /* GPIO6. */
static void enable_int_gfx(void) static void enable_int_gfx(void)

4
src/mainboard/amd/bettong/BiosCallOuts.c
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@ -24,8 +24,8 @@
#include "hudson.h" #include "hudson.h"
#include <stdlib.h> #include <stdlib.h>
#include <string.h> #include <string.h>
#include "northbridge/amd/pi/dimmSpd.h" #include <northbridge/amd/pi/dimmSpd.h>
#include "northbridge/amd/pi/agesawrapper.h" #include <northbridge/amd/pi/agesawrapper.h>
#include <boardid.h> #include <boardid.h>
static AGESA_STATUS Fch_Oem_config(UINT32 Func, UINTN FchData, VOID *ConfigPtr); static AGESA_STATUS Fch_Oem_config(UINT32 Func, UINTN FchData, VOID *ConfigPtr);

2
src/mainboard/amd/bettong/mptable.c
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@ -22,7 +22,7 @@
#include <stdint.h> #include <stdint.h>
#include <arch/cpu.h> #include <arch/cpu.h>
#include <cpu/x86/lapic.h> #include <cpu/x86/lapic.h>
#include "southbridge/amd/pi/hudson/hudson.h" #include <southbridge/amd/pi/hudson/hudson.h>
#include <southbridge/amd/common/amd_pci_util.h> #include <southbridge/amd/common/amd_pci_util.h>
static void smp_add_mpc_entry(struct mp_config_table *mc, unsigned length) static void smp_add_mpc_entry(struct mp_config_table *mc, unsigned length)

4
src/mainboard/amd/bimini_fam10/mainboard.c
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@ -17,12 +17,10 @@
#include <device/device.h> #include <device/device.h>
#include <device/pci.h> #include <device/pci.h>
#include <arch/io.h> #include <arch/io.h>
#include <cpu/x86/msr.h>
#include <cpu/amd/mtrr.h>
#include <device/pci_def.h> #include <device/pci_def.h>
#include <southbridge/amd/common/amd_defs.h> #include <southbridge/amd/common/amd_defs.h>
#include <southbridge/amd/sb800/sb800.h> #include <southbridge/amd/sb800/sb800.h>
#include "southbridge/amd/rs780/rs780.h" #include <southbridge/amd/rs780/rs780.h>
/* GPIO6. */ /* GPIO6. */
static void enable_int_gfx(void) static void enable_int_gfx(void)

8
src/mainboard/amd/mahogany_fam10/mainboard.c
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@ -17,12 +17,10 @@
#include <device/device.h> #include <device/device.h>
#include <device/pci.h> #include <device/pci.h>
#include <arch/io.h> #include <arch/io.h>
#include <cpu/x86/msr.h>
#include <cpu/amd/mtrr.h>
#include <device/pci_def.h> #include <device/pci_def.h>
#include "southbridge/amd/sb700/sb700.h" #include <southbridge/amd/sb700/sb700.h>
#include "southbridge/amd/sb700/smbus.h" #include <southbridge/amd/sb700/smbus.h>
#include "southbridge/amd/rs780/rs780.h" #include <southbridge/amd/rs780/rs780.h>
/* /*
* Mahogany uses GPIO 6 as PCIe slot reset, GPIO4 as GFX slot reset. We need to * Mahogany uses GPIO 6 as PCIe slot reset, GPIO4 as GFX slot reset. We need to

3
src/mainboard/amd/olivehill/mptable.c
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@ -13,7 +13,6 @@
* GNU General Public License for more details. * GNU General Public License for more details.
*/ */
#include <console/console.h>
#include <arch/smp/mpspec.h> #include <arch/smp/mpspec.h>
#include <device/pci.h> #include <device/pci.h>
#include <arch/io.h> #include <arch/io.h>
@ -22,7 +21,7 @@
#include <stdint.h> #include <stdint.h>
#include <arch/cpu.h> #include <arch/cpu.h>
#include <cpu/x86/lapic.h> #include <cpu/x86/lapic.h>
#include "southbridge/amd/agesa/hudson/hudson.h" #include <southbridge/amd/agesa/hudson/hudson.h>
u8 picr_data[0x54] = { u8 picr_data[0x54] = {
0x03,0x04,0x05,0x07,0x0B,0x0A,0x1F,0x1F,0xFA,0xF1,0x00,0x00,0x1F,0x1F,0x1F,0x1F, 0x03,0x04,0x05,0x07,0x0B,0x0A,0x1F,0x1F,0xFA,0xF1,0x00,0x00,0x1F,0x1F,0x1F,0x1F,

3
src/mainboard/amd/parmer/mptable.c
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@ -13,7 +13,6 @@
* GNU General Public License for more details. * GNU General Public License for more details.
*/ */
#include <console/console.h>
#include <arch/smp/mpspec.h> #include <arch/smp/mpspec.h>
#include <device/pci.h> #include <device/pci.h>
#include <arch/io.h> #include <arch/io.h>
@ -22,7 +21,7 @@
#include <stdint.h> #include <stdint.h>
#include <arch/cpu.h> #include <arch/cpu.h>
#include <cpu/x86/lapic.h> #include <cpu/x86/lapic.h>
#include "southbridge/amd/agesa/hudson/hudson.h" #include <southbridge/amd/agesa/hudson/hudson.h>
u8 picr_data[0x54] = { u8 picr_data[0x54] = {
0x1F,0x1f,0x1f,0x1F,0x1F,0x1F,0x1F,0x1F,0x0A,0xF1,0x00,0x00,0x1F,0x1F,0x1F,0x1F, 0x1F,0x1f,0x1f,0x1F,0x1F,0x1F,0x1F,0x1F,0x0A,0xF1,0x00,0x00,0x1F,0x1F,0x1F,0x1F,

3
src/mainboard/amd/thatcher/mptable.c
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@ -13,7 +13,6 @@
* GNU General Public License for more details. * GNU General Public License for more details.
*/ */
#include <console/console.h>
#include <arch/smp/mpspec.h> #include <arch/smp/mpspec.h>
#include <device/pci.h> #include <device/pci.h>
#include <arch/io.h> #include <arch/io.h>
@ -22,7 +21,7 @@
#include <stdint.h> #include <stdint.h>
#include <arch/cpu.h> #include <arch/cpu.h>
#include <cpu/x86/lapic.h> #include <cpu/x86/lapic.h>
#include "southbridge/amd/agesa/hudson/hudson.h" #include <southbridge/amd/agesa/hudson/hudson.h>
u8 picr_data[] = { u8 picr_data[] = {
0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x0A,0xF1,0x00,0x00,0x1F,0x1F,0x1F,0x1F, 0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x0A,0xF1,0x00,0x00,0x1F,0x1F,0x1F,0x1F,

6
src/mainboard/amd/tilapia_fam10/mainboard.c
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@ -17,12 +17,10 @@
#include <device/device.h> #include <device/device.h>
#include <device/pci.h> #include <device/pci.h>
#include <arch/io.h> #include <arch/io.h>
#include <cpu/x86/msr.h>
#include <cpu/amd/mtrr.h>
#include <device/pci_def.h> #include <device/pci_def.h>
#include <southbridge/amd/sb700/sb700.h> #include <southbridge/amd/sb700/sb700.h>
#include "southbridge/amd/sb700/smbus.h" #include <southbridge/amd/sb700/smbus.h>
#include "southbridge/amd/rs780/rs780.h" #include <southbridge/amd/rs780/rs780.h>
#define ADT7461_ADDRESS 0x4C #define ADT7461_ADDRESS 0x4C
#define ARA_ADDRESS 0x0C /* Alert Response Address */ #define ARA_ADDRESS 0x0C /* Alert Response Address */

4
src/mainboard/apple/macbook21/smihandler.c
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@ -17,8 +17,8 @@
#include <arch/io.h> #include <arch/io.h>
#include <console/console.h> #include <console/console.h>
#include <cpu/x86/smm.h> #include <cpu/x86/smm.h>
#include "southbridge/intel/i82801gx/nvs.h" #include <southbridge/intel/i82801gx/nvs.h>
#include "southbridge/intel/i82801gx/i82801gx.h" #include <southbridge/intel/i82801gx/i82801gx.h>
#include <pc80/mc146818rtc.h> #include <pc80/mc146818rtc.h>
#include <delay.h> #include <delay.h>

13
src/mainboard/apple/macbookair4_2/early_southbridge.c
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@ -14,20 +14,13 @@
#include <stdint.h> #include <stdint.h>
#include <string.h> #include <string.h>
#include <lib.h> #include <lib.h>
#include <timestamp.h>
#include <arch/byteorder.h> #include <arch/byteorder.h>
#include <arch/io.h> #include <arch/io.h>
#include <device/pci_def.h> #include <device/pci_def.h>
#include <device/pnp_def.h> #include <device/pnp_def.h>
#include <cpu/x86/lapic.h> #include <northbridge/intel/sandybridge/sandybridge.h>
#include <arch/acpi.h> #include <northbridge/intel/sandybridge/raminit_native.h>
#include <console/console.h> #include <southbridge/intel/bd82x6x/pch.h>
#include "northbridge/intel/sandybridge/sandybridge.h"
#include "northbridge/intel/sandybridge/raminit_native.h"
#include "southbridge/intel/bd82x6x/pch.h"
#include <southbridge/intel/common/gpio.h>
#include <arch/cpu.h>
#include <cpu/x86/msr.h>
#include <cbfs.h> #include <cbfs.h>
void pch_enable_lpc(void) void pch_enable_lpc(void)

2
src/mainboard/asrock/b75pro3-m/romstage.c
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@ -14,7 +14,7 @@
* GNU General Public License for more details. * GNU General Public License for more details.
*/ */
#include "northbridge/intel/sandybridge/raminit_native.h" #include <northbridge/intel/sandybridge/raminit_native.h>
#include <superio/nuvoton/nct6776/nct6776.h> #include <superio/nuvoton/nct6776/nct6776.h>
#include <superio/nuvoton/common/nuvoton.h> #include <superio/nuvoton/common/nuvoton.h>

3
src/mainboard/asrock/imb-a180/mptable.c
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@ -13,7 +13,6 @@
* GNU General Public License for more details. * GNU General Public License for more details.
*/ */
#include <console/console.h>
#include <arch/smp/mpspec.h> #include <arch/smp/mpspec.h>
#include <device/pci.h> #include <device/pci.h>
#include <arch/io.h> #include <arch/io.h>
@ -22,7 +21,7 @@
#include <stdint.h> #include <stdint.h>
#include <arch/cpu.h> #include <arch/cpu.h>
#include <cpu/x86/lapic.h> #include <cpu/x86/lapic.h>
#include "southbridge/amd/agesa/hudson/hudson.h" #include <southbridge/amd/agesa/hudson/hudson.h>
u8 picr_data[0x54] = { u8 picr_data[0x54] = {

2
src/mainboard/asus/f2a85-m/mptable.c
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@ -21,7 +21,7 @@
#include <device/pci.h> #include <device/pci.h>
#include <stdint.h> #include <stdint.h>
#include <string.h> #include <string.h>
#include "southbridge/amd/agesa/hudson/hudson.h" #include <southbridge/amd/agesa/hudson/hudson.h>
u8 picr_data[] = { u8 picr_data[] = {

8
src/mainboard/asus/m4a78-em/mainboard.c
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@ -17,12 +17,10 @@
#include <device/device.h> #include <device/device.h>
#include <device/pci.h> #include <device/pci.h>
#include <arch/io.h> #include <arch/io.h>
#include <cpu/x86/msr.h>
#include <cpu/amd/mtrr.h>
#include <device/pci_def.h> #include <device/pci_def.h>
#include "southbridge/amd/sb700/sb700.h" #include <southbridge/amd/sb700/sb700.h>
#include "southbridge/amd/sb700/smbus.h" #include <southbridge/amd/sb700/smbus.h>
#include "southbridge/amd/rs780/rs780.h" #include <southbridge/amd/rs780/rs780.h>
void set_pcie_dereset(void) void set_pcie_dereset(void)
{ {

8
src/mainboard/asus/m4a785-m/mainboard.c
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@ -17,12 +17,10 @@
#include <device/device.h> #include <device/device.h>
#include <device/pci.h> #include <device/pci.h>
#include <arch/io.h> #include <arch/io.h>
#include <cpu/x86/msr.h>
#include <cpu/amd/mtrr.h>
#include <device/pci_def.h> #include <device/pci_def.h>
#include "southbridge/amd/sb700/sb700.h" #include <southbridge/amd/sb700/sb700.h>
#include "southbridge/amd/sb700/smbus.h" #include <southbridge/amd/sb700/smbus.h>
#include "southbridge/amd/rs780/rs780.h" #include <southbridge/amd/rs780/rs780.h>
#define ADT7461_ADDRESS 0x4C #define ADT7461_ADDRESS 0x4C
#define ARA_ADDRESS 0x0C /* Alert Response Address */ #define ARA_ADDRESS 0x0C /* Alert Response Address */

4
src/mainboard/asus/m5a88-v/mainboard.c
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@ -17,11 +17,9 @@
#include <device/device.h> #include <device/device.h>
#include <device/pci.h> #include <device/pci.h>
#include <arch/io.h> #include <arch/io.h>
#include <cpu/x86/msr.h>
#include <cpu/amd/mtrr.h>
#include <southbridge/amd/common/amd_defs.h> #include <southbridge/amd/common/amd_defs.h>
#include <device/pci_def.h> #include <device/pci_def.h>
#include "southbridge/amd/rs780/rs780.h" #include <southbridge/amd/rs780/rs780.h>
/* GPIO6. */ /* GPIO6. */
static void enable_int_gfx(void) static void enable_int_gfx(void)

2
src/mainboard/asus/p2b-ls/dsdt.asl
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@ -13,7 +13,7 @@
* GNU General Public License for more details. * GNU General Public License for more details.
*/ */
#include "southbridge/intel/i82371eb/i82371eb.h" #include <southbridge/intel/i82371eb/i82371eb.h>
#define SUPERIO_PNP_BASE 0x3F0 #define SUPERIO_PNP_BASE 0x3F0
#define SUPERIO_SHOW_UARTA #define SUPERIO_SHOW_UARTA

2
src/mainboard/asus/p2b/dsdt.asl
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@ -14,7 +14,7 @@
* GNU General Public License for more details. * GNU General Public License for more details.
*/ */
#include "southbridge/intel/i82371eb/i82371eb.h" #include <southbridge/intel/i82371eb/i82371eb.h>
#define SUPERIO_PNP_BASE 0x3F0 #define SUPERIO_PNP_BASE 0x3F0
#define SUPERIO_SHOW_UARTA #define SUPERIO_SHOW_UARTA

2
src/mainboard/asus/p5gc-mx/acpi_tables.c
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@ -15,7 +15,7 @@
#include <types.h> #include <types.h>
#include "southbridge/intel/i82801gx/nvs.h" #include <southbridge/intel/i82801gx/nvs.h>
void acpi_create_gnvs(global_nvs_t *gnvs) void acpi_create_gnvs(global_nvs_t *gnvs)
{ {

4
src/mainboard/avalue/eax-785e/mainboard.c
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@ -17,11 +17,9 @@
#include <device/device.h> #include <device/device.h>
#include <device/pci.h> #include <device/pci.h>
#include <arch/io.h> #include <arch/io.h>
#include <cpu/x86/msr.h>
#include <cpu/amd/mtrr.h>
#include <southbridge/amd/common/amd_defs.h> #include <southbridge/amd/common/amd_defs.h>
#include <device/pci_def.h> #include <device/pci_def.h>
#include "southbridge/amd/rs780/rs780.h" #include <southbridge/amd/rs780/rs780.h>
/* GPIO6. */ /* GPIO6. */
static void enable_int_gfx(void) static void enable_int_gfx(void)

2
src/mainboard/avalue/eax-785e/romstage.c
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@ -45,7 +45,7 @@
#include "spd.h" #include "spd.h"
#include <reset.h> #include <reset.h>
#include <southbridge/amd/rs780/rs780.h> #include <southbridge/amd/rs780/rs780.h>
#include "southbridge/amd/sb800/early_setup.c" #include <southbridge/amd/sb800/early_setup.c>
#include "resourcemap.c" #include "resourcemap.c"
#include "cpu/amd/quadcore/quadcore.c" #include "cpu/amd/quadcore/quadcore.c"

3
src/mainboard/biostar/a68n_5200/mptable.c
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@ -13,7 +13,6 @@
* GNU General Public License for more details. * GNU General Public License for more details.
*/ */
#include <console/console.h>
#include <arch/smp/mpspec.h> #include <arch/smp/mpspec.h>
#include <device/pci.h> #include <device/pci.h>
#include <arch/io.h> #include <arch/io.h>
@ -22,7 +21,7 @@
#include <stdint.h> #include <stdint.h>
#include <arch/cpu.h> #include <arch/cpu.h>
#include <cpu/x86/lapic.h> #include <cpu/x86/lapic.h>
#include "southbridge/amd/agesa/hudson/hudson.h" #include <southbridge/amd/agesa/hudson/hudson.h>
u8 picr_data[0x54] = { u8 picr_data[0x54] = {
0x03,0x04,0x05,0x07,0x0B,0x0A,0x1F,0x1F,0xFA,0xF1,0x00,0x00,0x1F,0x1F,0x1F,0x1F, 0x03,0x04,0x05,0x07,0x0B,0x0A,0x1F,0x1F,0xFA,0xF1,0x00,0x00,0x1F,0x1F,0x1F,0x1F,

2
src/mainboard/compulab/intense_pc/romstage.c
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@ -16,7 +16,7 @@
#include <stdint.h> #include <stdint.h>
#include <lib.h> #include <lib.h>
#include <arch/io.h> #include <arch/io.h>
#include "northbridge/intel/sandybridge/raminit_native.h" #include <northbridge/intel/sandybridge/raminit_native.h>
#include <superio/smsc/sio1007/chip.h> #include <superio/smsc/sio1007/chip.h>
#define SIO_PORT 0x164e #define SIO_PORT 0x164e

3
src/mainboard/emulation/qemu-q35/acpi_tables.c
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@ -15,7 +15,6 @@
#include <types.h> #include <types.h>
#include <string.h> #include <string.h>
#include <console/console.h>
#include <arch/acpi.h> #include <arch/acpi.h>
#include <arch/ioapic.h> #include <arch/ioapic.h>
#include <arch/acpigen.h> #include <arch/acpigen.h>
@ -26,7 +25,7 @@
#include "../qemu-i440fx/fw_cfg.h" #include "../qemu-i440fx/fw_cfg.h"
#include "../qemu-i440fx/acpi.h" #include "../qemu-i440fx/acpi.h"
#include "southbridge/intel/i82801ix/nvs.h" #include <southbridge/intel/i82801ix/nvs.h>
void acpi_create_gnvs(global_nvs_t *gnvs) void acpi_create_gnvs(global_nvs_t *gnvs)
{ {

2
src/mainboard/getac/p470/acpi_tables.c
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@ -25,7 +25,7 @@
#include <device/pci.h> #include <device/pci.h>
#include <device/pci_ids.h> #include <device/pci_ids.h>
#include "southbridge/intel/i82801gx/nvs.h" #include <southbridge/intel/i82801gx/nvs.h>
#include "mainboard.h" #include "mainboard.h"
void acpi_create_gnvs(global_nvs_t *gnvs) void acpi_create_gnvs(global_nvs_t *gnvs)

4
src/mainboard/getac/p470/smihandler.c
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@ -17,8 +17,8 @@
#include <arch/io.h> #include <arch/io.h>
#include <console/console.h> #include <console/console.h>
#include <cpu/x86/smm.h> #include <cpu/x86/smm.h>
#include "southbridge/intel/i82801gx/i82801gx.h" #include <southbridge/intel/i82801gx/i82801gx.h>
#include "southbridge/intel/i82801gx/nvs.h" #include <southbridge/intel/i82801gx/nvs.h>
#include <southbridge/intel/common/gpio.h> #include <southbridge/intel/common/gpio.h>
#include <ec/acpi/ec.h> #include <ec/acpi/ec.h>
#include "ec_oem.c" #include "ec_oem.c"

8
src/mainboard/gigabyte/ma785gm/mainboard.c
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@ -17,12 +17,10 @@
#include <device/device.h> #include <device/device.h>
#include <device/pci.h> #include <device/pci.h>
#include <arch/io.h> #include <arch/io.h>
#include <cpu/x86/msr.h>
#include <cpu/amd/mtrr.h>
#include <device/pci_def.h> #include <device/pci_def.h>
#include "southbridge/amd/sb700/sb700.h" #include <southbridge/amd/sb700/sb700.h>
#include "southbridge/amd/sb700/smbus.h" #include <southbridge/amd/sb700/smbus.h>
#include "southbridge/amd/rs780/rs780.h" #include <southbridge/amd/rs780/rs780.h>
void set_pcie_dereset(void) void set_pcie_dereset(void)
{ {

8
src/mainboard/gigabyte/ma785gmt/mainboard.c
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@ -17,12 +17,10 @@
#include <device/device.h> #include <device/device.h>
#include <device/pci.h> #include <device/pci.h>
#include <arch/io.h> #include <arch/io.h>
#include <cpu/x86/msr.h>
#include <cpu/amd/mtrr.h>
#include <device/pci_def.h> #include <device/pci_def.h>
#include "southbridge/amd/sb700/sb700.h" #include <southbridge/amd/sb700/sb700.h>
#include "southbridge/amd/sb700/smbus.h" #include <southbridge/amd/sb700/smbus.h>
#include "southbridge/amd/rs780/rs780.h" #include <southbridge/amd/rs780/rs780.h>
#define ADT7461_ADDRESS 0x4C #define ADT7461_ADDRESS 0x4C
#define ARA_ADDRESS 0x0C /* Alert Response Address */ #define ARA_ADDRESS 0x0C /* Alert Response Address */

8
src/mainboard/gigabyte/ma78gm/mainboard.c
View File

@ -18,12 +18,10 @@
#include <device/device.h> #include <device/device.h>
#include <device/pci.h> #include <device/pci.h>
#include <arch/io.h> #include <arch/io.h>
#include <cpu/x86/msr.h>
#include <cpu/amd/mtrr.h>
#include <device/pci_def.h> #include <device/pci_def.h>
#include "southbridge/amd/sb700/sb700.h" #include <southbridge/amd/sb700/sb700.h>
#include "southbridge/amd/sb700/smbus.h" #include <southbridge/amd/sb700/smbus.h>
#include "southbridge/amd/rs780/rs780.h" #include <southbridge/amd/rs780/rs780.h>
/* /*
* ma78gm-us2h uses GPIO 6 as PCIe slot reset, GPIO4 as GFX slot reset. We need to * ma78gm-us2h uses GPIO 6 as PCIe slot reset, GPIO4 as GFX slot reset. We need to

3
src/mainboard/hp/abm/mptable.c
View File

@ -13,7 +13,6 @@
* GNU General Public License for more details. * GNU General Public License for more details.
*/ */
#include <console/console.h>
#include <arch/smp/mpspec.h> #include <arch/smp/mpspec.h>
#include <device/pci.h> #include <device/pci.h>
#include <arch/io.h> #include <arch/io.h>
@ -22,7 +21,7 @@
#include <stdint.h> #include <stdint.h>
#include <arch/cpu.h> #include <arch/cpu.h>
#include <cpu/x86/lapic.h> #include <cpu/x86/lapic.h>
#include "southbridge/amd/agesa/hudson/hudson.h" #include <southbridge/amd/agesa/hudson/hudson.h>
u8 picr_data[0x54] = { u8 picr_data[0x54] = {

6
src/mainboard/hp/compaq_8200_elite_sff/romstage.c
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@ -23,9 +23,9 @@
#include <device/pnp_def.h> #include <device/pnp_def.h>
#include <superio/nuvoton/npcd378/npcd378.h> #include <superio/nuvoton/npcd378/npcd378.h>
#include <superio/nuvoton/common/nuvoton.h> #include <superio/nuvoton/common/nuvoton.h>
#include "northbridge/intel/sandybridge/sandybridge.h" #include <northbridge/intel/sandybridge/sandybridge.h>
#include "northbridge/intel/sandybridge/raminit_native.h" #include <northbridge/intel/sandybridge/raminit_native.h>
#include "southbridge/intel/bd82x6x/pch.h" #include <southbridge/intel/bd82x6x/pch.h>
#define SERIAL_DEV PNP_DEV(0x2e, NPCD378_SP2) #define SERIAL_DEV PNP_DEV(0x2e, NPCD378_SP2)

8
src/mainboard/iei/kino-780am2-fam10/mainboard.c
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@ -17,12 +17,10 @@
#include <device/device.h> #include <device/device.h>
#include <device/pci.h> #include <device/pci.h>
#include <arch/io.h> #include <arch/io.h>
#include <cpu/x86/msr.h>
#include <cpu/amd/mtrr.h>
#include <device/pci_def.h> #include <device/pci_def.h>
#include "southbridge/amd/sb700/sb700.h" #include <southbridge/amd/sb700/sb700.h>
#include "southbridge/amd/sb700/smbus.h" #include <southbridge/amd/sb700/smbus.h>
#include "southbridge/amd/rs780/rs780.h" #include <southbridge/amd/rs780/rs780.h>
/* TODO - Need to find GPIO for PCIE slot. /* TODO - Need to find GPIO for PCIE slot.
* Kino uses GPIO ? as PCIe slot reset, GPIO? as GFX slot reset. We need to * Kino uses GPIO ? as PCIe slot reset, GPIO? as GFX slot reset. We need to

3
src/mainboard/intel/cougar_canyon2/acpi_tables.c
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@ -16,7 +16,6 @@
#include <types.h> #include <types.h>
#include <string.h> #include <string.h>
#include <cbmem.h> #include <cbmem.h>
#include <console/console.h>
#include <arch/acpi.h> #include <arch/acpi.h>
#include <arch/ioapic.h> #include <arch/ioapic.h>
#include <arch/acpigen.h> #include <arch/acpigen.h>
@ -24,8 +23,8 @@
#include <device/device.h> #include <device/device.h>
#include <device/pci.h> #include <device/pci.h>
#include <device/pci_ids.h> #include <device/pci_ids.h>
#include <southbridge/intel/fsp_bd82x6x/nvs.h>
#include "southbridge/intel/fsp_bd82x6x/nvs.h"
#include "thermal.h" #include "thermal.h"
static global_nvs_t *gnvs_; static global_nvs_t *gnvs_;

2
src/mainboard/intel/cougar_canyon2/gpio.h
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@ -17,7 +17,7 @@
#ifndef MAINBOARD_GPIO_H #ifndef MAINBOARD_GPIO_H
#define MAINBOARD_GPIO_H #define MAINBOARD_GPIO_H
#include "southbridge/intel/fsp_bd82x6x/gpio.h" #include <southbridge/intel/fsp_bd82x6x/gpio.h>
const struct pch_gpio_set1 pch_gpio_set1_mode = { const struct pch_gpio_set1 pch_gpio_set1_mode = {
.gpio0 = GPIO_MODE_GPIO, /* SINAI */ .gpio0 = GPIO_MODE_GPIO, /* SINAI */

2
src/mainboard/intel/dcp847ske/early_southbridge.c
View File

@ -22,7 +22,7 @@
#include <device/pci_def.h> #include <device/pci_def.h>
#include <arch/acpi.h> #include <arch/acpi.h>
#include <console/console.h> #include <console/console.h>
#include "northbridge/intel/sandybridge/raminit_native.h" #include <northbridge/intel/sandybridge/raminit_native.h>
#include "superio.h" #include "superio.h"
#include "thermal.h" #include "thermal.h"

3
src/mainboard/intel/dg41wv/acpi_tables.c
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@ -16,8 +16,7 @@
#include <string.h> #include <string.h>
#include <stdint.h> #include <stdint.h>
#include <southbridge/intel/i82801gx/nvs.h>
#include "southbridge/intel/i82801gx/nvs.h"
void acpi_create_gnvs(global_nvs_t *gnvs) void acpi_create_gnvs(global_nvs_t *gnvs)
{ {

3
src/mainboard/intel/emeraldlake2/acpi_tables.c
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@ -16,7 +16,6 @@
#include <types.h> #include <types.h>
#include <string.h> #include <string.h>
#include <cbmem.h> #include <cbmem.h>
#include <console/console.h>
#include <arch/acpi.h> #include <arch/acpi.h>
#include <arch/ioapic.h> #include <arch/ioapic.h>
#include <arch/acpigen.h> #include <arch/acpigen.h>
@ -25,8 +24,8 @@
#include <device/pci.h> #include <device/pci.h>
#include <device/pci_ids.h> #include <device/pci_ids.h>
#include <vendorcode/google/chromeos/gnvs.h> #include <vendorcode/google/chromeos/gnvs.h>
#include <southbridge/intel/bd82x6x/nvs.h>
#include "southbridge/intel/bd82x6x/nvs.h"
#include "thermal.h" #include "thermal.h"
static global_nvs_t *gnvs_; static global_nvs_t *gnvs_;

2
src/mainboard/intel/stargo2/gpio.h
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@ -17,7 +17,7 @@
#ifndef MAINBOARD_GPIO_H #ifndef MAINBOARD_GPIO_H
#define MAINBOARD_GPIO_H #define MAINBOARD_GPIO_H
#include "southbridge/intel/fsp_i89xx/gpio.h" #include <southbridge/intel/fsp_i89xx/gpio.h>
const struct pch_gpio_set1 pch_gpio_set1_mode = { const struct pch_gpio_set1 pch_gpio_set1_mode = {

8
src/mainboard/jetway/pa78vm5/mainboard.c
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@ -18,12 +18,10 @@
#include <device/device.h> #include <device/device.h>
#include <device/pci.h> #include <device/pci.h>
#include <arch/io.h> #include <arch/io.h>
#include <cpu/x86/msr.h>
#include <cpu/amd/mtrr.h>
#include <device/pci_def.h> #include <device/pci_def.h>
#include "southbridge/amd/sb700/sb700.h" #include <southbridge/amd/sb700/sb700.h>
#include "southbridge/amd/sb700/smbus.h" #include <southbridge/amd/sb700/smbus.h>
#include "southbridge/amd/rs780/rs780.h" #include <southbridge/amd/rs780/rs780.h>
/* /*
* the board uses GPIO 6 as PCIe slot reset, GPIO4 as GFX slot reset. We need to * the board uses GPIO 6 as PCIe slot reset, GPIO4 as GFX slot reset. We need to

11
src/mainboard/lenovo/s230u/romstage.c
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@ -17,20 +17,15 @@
#include <string.h> #include <string.h>
#include <cbfs.h> #include <cbfs.h>
#include <lib.h> #include <lib.h>
#include <timestamp.h>
#include <arch/byteorder.h> #include <arch/byteorder.h>
#include <arch/io.h> #include <arch/io.h>
#include <device/pci_def.h> #include <device/pci_def.h>
#include <device/pnp_def.h> #include <device/pnp_def.h>
#include <cpu/x86/lapic.h>
#include <arch/acpi.h>
#include <console/console.h> #include <console/console.h>
#include "northbridge/intel/sandybridge/sandybridge.h" #include <northbridge/intel/sandybridge/sandybridge.h>
#include "northbridge/intel/sandybridge/raminit_native.h" #include <northbridge/intel/sandybridge/raminit_native.h>
#include "southbridge/intel/bd82x6x/pch.h" #include <southbridge/intel/bd82x6x/pch.h>
#include <southbridge/intel/common/gpio.h> #include <southbridge/intel/common/gpio.h>
#include <arch/cpu.h>
#include <cpu/x86/msr.h>
#include "ec.h" #include "ec.h"
#define SPD_LEN 256 #define SPD_LEN 256

4
src/mainboard/lenovo/t400/acpi_tables.c
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@ -15,7 +15,6 @@
*/ */
#include <string.h> #include <string.h>
#include <console/console.h>
#include <arch/io.h> #include <arch/io.h>
#include <arch/ioapic.h> #include <arch/ioapic.h>
#include <arch/acpi.h> #include <arch/acpi.h>
@ -24,8 +23,7 @@
#include <device/device.h> #include <device/device.h>
#include <device/pci.h> #include <device/pci.h>
#include <device/pci_ids.h> #include <device/pci_ids.h>
#include <southbridge/intel/i82801ix/nvs.h>
#include "southbridge/intel/i82801ix/nvs.h"
void acpi_create_gnvs(global_nvs_t *gnvs) void acpi_create_gnvs(global_nvs_t *gnvs)
{ {

2
src/mainboard/lenovo/t400/dock.c
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@ -25,7 +25,7 @@
#include "dock.h" #include "dock.h"
#include <superio/nsc/pc87382/pc87382.h> #include <superio/nsc/pc87382/pc87382.h>
#include "southbridge/intel/i82801ix/i82801ix.h" #include <southbridge/intel/i82801ix/i82801ix.h>
#include "ec/lenovo/h8/h8.h" #include "ec/lenovo/h8/h8.h"
#include <ec/acpi/ec.h> #include <ec/acpi/ec.h>

3
src/mainboard/lenovo/t60/dock.c
View File

@ -14,7 +14,6 @@
* GNU General Public License for more details. * GNU General Public License for more details.
*/ */
#include <console/console.h>
#include <device/device.h> #include <device/device.h>
#include <arch/io.h> #include <arch/io.h>
#include <delay.h> #include <delay.h>
@ -22,7 +21,7 @@
#include <superio/nsc/pc87384/pc87384.h> #include <superio/nsc/pc87384/pc87384.h>
#include "ec/acpi/ec.h" #include "ec/acpi/ec.h"
#include "ec/lenovo/pmh7/pmh7.h" #include "ec/lenovo/pmh7/pmh7.h"
#include "southbridge/intel/i82801gx/i82801gx.h" #include <southbridge/intel/i82801gx/i82801gx.h>
#define DLPC_CONTROL 0x164c #define DLPC_CONTROL 0x164c

4
src/mainboard/lenovo/t60/smihandler.c
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@ -17,8 +17,8 @@
#include <arch/io.h> #include <arch/io.h>
#include <console/console.h> #include <console/console.h>
#include <cpu/x86/smm.h> #include <cpu/x86/smm.h>
#include "southbridge/intel/i82801gx/nvs.h" #include <southbridge/intel/i82801gx/nvs.h>
#include "southbridge/intel/i82801gx/i82801gx.h" #include <southbridge/intel/i82801gx/i82801gx.h>
#include <ec/acpi/ec.h> #include <ec/acpi/ec.h>
#include "dock.h" #include "dock.h"
#include "smi.h" #include "smi.h"

3
src/mainboard/lenovo/x200/acpi_tables.c
View File

@ -15,7 +15,6 @@
*/ */
#include <string.h> #include <string.h>
#include <console/console.h>
#include <arch/io.h> #include <arch/io.h>
#include <arch/ioapic.h> #include <arch/ioapic.h>
#include <arch/acpi.h> #include <arch/acpi.h>
@ -24,8 +23,8 @@
#include <device/device.h> #include <device/device.h>
#include <device/pci.h> #include <device/pci.h>
#include <device/pci_ids.h> #include <device/pci_ids.h>
#include <southbridge/intel/i82801ix/nvs.h>
#include "southbridge/intel/i82801ix/nvs.h"
void acpi_create_gnvs(global_nvs_t *gnvs) void acpi_create_gnvs(global_nvs_t *gnvs)
{ {
memset((void *)gnvs, 0, sizeof(*gnvs)); memset((void *)gnvs, 0, sizeof(*gnvs));

2
src/mainboard/lenovo/x200/dock.c
View File

@ -22,7 +22,7 @@
#include <device/pci.h> #include <device/pci.h>
#include <delay.h> #include <delay.h>
#include "dock.h" #include "dock.h"
#include "southbridge/intel/i82801ix/i82801ix.h" #include <southbridge/intel/i82801ix/i82801ix.h>
#include "ec/lenovo/h8/h8.h" #include "ec/lenovo/h8/h8.h"
#include <ec/acpi/ec.h> #include <ec/acpi/ec.h>

2
src/mainboard/lenovo/x201/dock.c
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@ -22,7 +22,7 @@
#include <device/pci.h> #include <device/pci.h>
#include <delay.h> #include <delay.h>
#include "dock.h" #include "dock.h"
#include "southbridge/intel/ibexpeak/pch.h" #include <southbridge/intel/ibexpeak/pch.h>
#include "ec/lenovo/h8/h8.h" #include "ec/lenovo/h8/h8.h"
#include <ec/acpi/ec.h> #include <ec/acpi/ec.h>

6
src/mainboard/lenovo/x201/smihandler.c
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@ -17,9 +17,9 @@
#include <arch/io.h> #include <arch/io.h>
#include <console/console.h> #include <console/console.h>
#include <cpu/x86/smm.h> #include <cpu/x86/smm.h>
#include "southbridge/intel/ibexpeak/nvs.h" #include <southbridge/intel/ibexpeak/nvs.h>
#include "southbridge/intel/ibexpeak/pch.h" #include <southbridge/intel/ibexpeak/pch.h>
#include "southbridge/intel/ibexpeak/me.h" #include <southbridge/intel/ibexpeak/me.h>
#include <northbridge/intel/nehalem/nehalem.h> #include <northbridge/intel/nehalem/nehalem.h>
#include <cpu/intel/model_2065x/model_2065x.h> #include <cpu/intel/model_2065x/model_2065x.h>
#include <ec/acpi/ec.h> #include <ec/acpi/ec.h>

2
src/mainboard/lenovo/x60/dock.c
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@ -20,7 +20,7 @@
#include <delay.h> #include <delay.h>
#include <arch/io.h> #include <arch/io.h>
#include "dock.h" #include "dock.h"
#include "southbridge/intel/i82801gx/i82801gx.h" #include <southbridge/intel/i82801gx/i82801gx.h>
#include <superio/nsc/pc87392/pc87392.h> #include <superio/nsc/pc87392/pc87392.h>
static void dlpc_write_register(int reg, int value) static void dlpc_write_register(int reg, int value)

4
src/mainboard/lenovo/x60/smihandler.c
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@ -17,8 +17,8 @@
#include <arch/io.h> #include <arch/io.h>
#include <console/console.h> #include <console/console.h>
#include <cpu/x86/smm.h> #include <cpu/x86/smm.h>
#include "southbridge/intel/i82801gx/nvs.h" #include <southbridge/intel/i82801gx/nvs.h>
#include "southbridge/intel/i82801gx/i82801gx.h" #include <southbridge/intel/i82801gx/i82801gx.h>
#include <ec/acpi/ec.h> #include <ec/acpi/ec.h>
#include <pc80/mc146818rtc.h> #include <pc80/mc146818rtc.h>
#include <ec/lenovo/h8/h8.h> #include <ec/lenovo/h8/h8.h>

3
src/mainboard/lenovo/z61t/dock.c
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@ -14,7 +14,6 @@
* GNU General Public License for more details. * GNU General Public License for more details.
*/ */
#include <console/console.h>
#include <device/device.h> #include <device/device.h>
#include <arch/io.h> #include <arch/io.h>
#include <delay.h> #include <delay.h>
@ -22,7 +21,7 @@
#include <superio/nsc/pc87384/pc87384.h> #include <superio/nsc/pc87384/pc87384.h>
#include "ec/acpi/ec.h" #include "ec/acpi/ec.h"
#include "ec/lenovo/pmh7/pmh7.h" #include "ec/lenovo/pmh7/pmh7.h"
#include "southbridge/intel/i82801gx/i82801gx.h" #include <southbridge/intel/i82801gx/i82801gx.h>
#define DLPC_CONTROL 0x164c #define DLPC_CONTROL 0x164c

4
src/mainboard/lenovo/z61t/smihandler.c
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@ -17,8 +17,8 @@
#include <arch/io.h> #include <arch/io.h>
#include <console/console.h> #include <console/console.h>
#include <cpu/x86/smm.h> #include <cpu/x86/smm.h>
#include "southbridge/intel/i82801gx/nvs.h" #include <southbridge/intel/i82801gx/nvs.h>
#include "southbridge/intel/i82801gx/i82801gx.h" #include <southbridge/intel/i82801gx/i82801gx.h>
#include <ec/acpi/ec.h> #include <ec/acpi/ec.h>
#include "dock.h" #include "dock.h"
#include "smi.h" #include "smi.h"

2
src/mainboard/msi/ms7721/mptable.c
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@ -21,7 +21,7 @@
#include <device/pci.h> #include <device/pci.h>
#include <stdint.h> #include <stdint.h>
#include <string.h> #include <string.h>
#include "southbridge/amd/agesa/hudson/hudson.h" #include <southbridge/amd/agesa/hudson/hudson.h>
u8 picr_data[] = { u8 picr_data[] = {

6
src/mainboard/packardbell/ms2290/smihandler.c
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@ -17,9 +17,9 @@
#include <arch/io.h> #include <arch/io.h>
#include <console/console.h> #include <console/console.h>
#include <cpu/x86/smm.h> #include <cpu/x86/smm.h>
#include "southbridge/intel/ibexpeak/nvs.h" #include <southbridge/intel/ibexpeak/nvs.h>
#include "southbridge/intel/ibexpeak/pch.h" #include <southbridge/intel/ibexpeak/pch.h>
#include "southbridge/intel/ibexpeak/me.h" #include <southbridge/intel/ibexpeak/me.h>
#include <northbridge/intel/nehalem/nehalem.h> #include <northbridge/intel/nehalem/nehalem.h>
#include <cpu/intel/model_2065x/model_2065x.h> #include <cpu/intel/model_2065x/model_2065x.h>
#include <ec/acpi/ec.h> #include <ec/acpi/ec.h>

3
src/mainboard/pcengines/alix2d/irq_tables.c
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@ -14,9 +14,8 @@
*/ */
#include <arch/pirq_routing.h> #include <arch/pirq_routing.h>
#include <console/console.h>
#include <arch/io.h> #include <arch/io.h>
#include "southbridge/amd/cs5536/cs5536.h" #include <southbridge/amd/cs5536/cs5536.h>
/* Platform IRQs */ /* Platform IRQs */
#define PIRQA 11 #define PIRQA 11

3
src/mainboard/roda/rk9/acpi_tables.c
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@ -15,7 +15,6 @@
*/ */
#include <string.h> #include <string.h>
#include <console/console.h>
#include <arch/io.h> #include <arch/io.h>
#include <arch/ioapic.h> #include <arch/ioapic.h>
#include <arch/acpi.h> #include <arch/acpi.h>
@ -24,8 +23,8 @@
#include <device/device.h> #include <device/device.h>
#include <device/pci.h> #include <device/pci.h>
#include <device/pci_ids.h> #include <device/pci_ids.h>
#include <southbridge/intel/i82801ix/nvs.h>
#include "southbridge/intel/i82801ix/nvs.h"
void acpi_create_gnvs(global_nvs_t *gnvs) void acpi_create_gnvs(global_nvs_t *gnvs)
{ {
memset((void *)gnvs, 0, sizeof(*gnvs)); memset((void *)gnvs, 0, sizeof(*gnvs));

3
src/mainboard/samsung/lumpy/acpi_tables.c
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@ -16,7 +16,6 @@
#include <types.h> #include <types.h>
#include <string.h> #include <string.h>
#include <cbmem.h> #include <cbmem.h>
#include <console/console.h>
#include <arch/acpi.h> #include <arch/acpi.h>
#include <arch/ioapic.h> #include <arch/ioapic.h>
#include <arch/acpigen.h> #include <arch/acpigen.h>
@ -28,8 +27,8 @@
#if IS_ENABLED(CONFIG_CHROMEOS) #if IS_ENABLED(CONFIG_CHROMEOS)
#include <vendorcode/google/chromeos/gnvs.h> #include <vendorcode/google/chromeos/gnvs.h>
#endif #endif
#include <southbridge/intel/bd82x6x/nvs.h>
#include "southbridge/intel/bd82x6x/nvs.h"
#include "thermal.h" #include "thermal.h"
static global_nvs_t *gnvs_; static global_nvs_t *gnvs_;

3
src/mainboard/samsung/stumpy/acpi_tables.c
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@ -16,7 +16,6 @@
#include <types.h> #include <types.h>
#include <string.h> #include <string.h>
#include <cbmem.h> #include <cbmem.h>
#include <console/console.h>
#include <arch/acpi.h> #include <arch/acpi.h>
#include <arch/ioapic.h> #include <arch/ioapic.h>
#include <arch/acpigen.h> #include <arch/acpigen.h>
@ -25,8 +24,8 @@
#include <device/pci.h> #include <device/pci.h>
#include <device/pci_ids.h> #include <device/pci_ids.h>
#include <vendorcode/google/chromeos/gnvs.h> #include <vendorcode/google/chromeos/gnvs.h>
#include <southbridge/intel/bd82x6x/nvs.h>
#include "southbridge/intel/bd82x6x/nvs.h"
#include "thermal.h" #include "thermal.h"
static global_nvs_t *gnvs_; static global_nvs_t *gnvs_;

15
src/mainboard/sapphire/pureplatinumh61/romstage.c
View File

@ -17,21 +17,14 @@
#include <stdint.h> #include <stdint.h>
#include <string.h> #include <string.h>
#include <lib.h> #include <lib.h>
#include <timestamp.h>
#include <arch/byteorder.h> #include <arch/byteorder.h>
#include <arch/io.h> #include <arch/io.h>
#include <device/pci_def.h> #include <device/pci_def.h>
#include <device/pnp_def.h> #include <device/pnp_def.h>
#include <cpu/x86/lapic.h> #include <northbridge/intel/sandybridge/sandybridge.h>
#include <arch/acpi.h> #include <northbridge/intel/sandybridge/raminit_native.h>
#include <console/console.h> #include <southbridge/intel/bd82x6x/pch.h>
#include "northbridge/intel/sandybridge/sandybridge.h"
#include "northbridge/intel/sandybridge/raminit_native.h"
#include "southbridge/intel/bd82x6x/pch.h"
#include <southbridge/intel/common/gpio.h>
#include <arch/cpu.h>
#include <cpu/x86/msr.h>
#include <delay.h>
void pch_enable_lpc(void) void pch_enable_lpc(void)
{ {