diff --git a/src/southbridge/intel/bd82x6x/azalia.c b/src/southbridge/intel/bd82x6x/azalia.c
index 02165d6c7f..0cbf3c6880 100644
--- a/src/southbridge/intel/bd82x6x/azalia.c
+++ b/src/southbridge/intel/bd82x6x/azalia.c
@@ -337,7 +337,8 @@ static const char *azalia_acpi_name(const struct device *dev)
 	return "HDEF";
 }
 
-static void azalia_set_subsystem(device_t dev, unsigned vendor, unsigned device)
+static void azalia_set_subsystem(struct device *dev, unsigned vendor,
+				 unsigned device)
 {
 	if (!vendor || !device) {
 		pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID,
diff --git a/src/southbridge/intel/bd82x6x/lpc.c b/src/southbridge/intel/bd82x6x/lpc.c
index ea7a80846c..109c06efd7 100644
--- a/src/southbridge/intel/bd82x6x/lpc.c
+++ b/src/southbridge/intel/bd82x6x/lpc.c
@@ -107,9 +107,9 @@ static void pch_enable_serial_irqs(struct device *dev)
  * 0x80 - The PIRQ is not routed.
  */
 
-static void pch_pirq_init(device_t dev)
+static void pch_pirq_init(struct device *dev)
 {
-	device_t irq_dev;
+	struct device *irq_dev;
 	/* Interrupt 11 is not used by legacy devices and so can always be used for
 	   PCI interrupts. Full legacy IRQ routing is complicated and hard to
 	   get right. Fortunately all modern OS use MSI and so it's not that big of
@@ -144,7 +144,7 @@ static void pch_pirq_init(device_t dev)
 	}
 }
 
-static void pch_gpi_routing(device_t dev)
+static void pch_gpi_routing(struct device *dev)
 {
 	/* Get the chip configuration */
 	config_t *config = dev->chip_info;
@@ -173,7 +173,7 @@ static void pch_gpi_routing(device_t dev)
 	pci_write_config32(dev, GPIO_ROUT, reg32);
 }
 
-static void pch_power_options(device_t dev)
+static void pch_power_options(struct device *dev)
 {
 	u8 reg8;
 	u16 reg16, pmbase;
@@ -396,7 +396,7 @@ static void enable_hpet(struct device *const dev)
 	RCBA32(HPTC) = reg32;
 }
 
-static void enable_clock_gating(device_t dev)
+static void enable_clock_gating(struct device *dev)
 {
 	u32 reg32;
 	u16 reg16;
@@ -561,7 +561,7 @@ static void lpc_init(struct device *dev)
 	pch_spi_init(dev);
 }
 
-static void pch_lpc_read_resources(device_t dev)
+static void pch_lpc_read_resources(struct device *dev)
 {
 	struct resource *res;
 	config_t *config = dev->chip_info;
@@ -625,13 +625,13 @@ static void pch_lpc_read_resources(device_t dev)
 	}
 }
 
-static void pch_lpc_enable_resources(device_t dev)
+static void pch_lpc_enable_resources(struct device *dev)
 {
 	pch_decode_init(dev);
 	return pci_dev_enable_resources(dev);
 }
 
-static void pch_lpc_enable(device_t dev)
+static void pch_lpc_enable(struct device *dev)
 {
 	/* Enable PCH Display Port */
 	RCBA16(DISPBDF) = 0x0010;
@@ -640,7 +640,7 @@ static void pch_lpc_enable(device_t dev)
 	pch_enable(dev);
 }
 
-static void set_subsystem(device_t dev, unsigned vendor, unsigned device)
+static void set_subsystem(struct device *dev, unsigned vendor, unsigned device)
 {
 	if (!vendor || !device) {
 		pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID,
@@ -651,7 +651,7 @@ static void set_subsystem(device_t dev, unsigned vendor, unsigned device)
 	}
 }
 
-static void southbridge_inject_dsdt(device_t dev)
+static void southbridge_inject_dsdt(struct device *dev)
 {
 	global_nvs_t *gnvs = cbmem_add (CBMEM_ID_ACPI_GNVS, sizeof(*gnvs));
 
@@ -684,7 +684,7 @@ static void southbridge_inject_dsdt(device_t dev)
 
 void acpi_fill_fadt(acpi_fadt_t *fadt)
 {
-	device_t dev = dev_find_slot(0, PCI_DEVFN(0x1f,0));
+	struct device *dev = dev_find_slot(0, PCI_DEVFN(0x1f, 0));
 	config_t *chip = dev->chip_info;
 	u16 pmbase = pci_read_config16(dev, 0x40) & 0xfffe;
 	int c2_latency;
@@ -819,9 +819,9 @@ static const char *lpc_acpi_name(const struct device *dev)
 	return "LPCB";
 }
 
-static void southbridge_fill_ssdt(device_t device)
+static void southbridge_fill_ssdt(struct device *device)
 {
-	device_t dev = dev_find_slot(0, PCI_DEVFN(0x1f,0));
+	struct device *dev = dev_find_slot(0, PCI_DEVFN(0x1f, 0));
 	config_t *chip = dev->chip_info;
 
 	intel_acpi_pcie_hotplug_generator(chip->pcie_hotplug_map, 8);
diff --git a/src/southbridge/intel/bd82x6x/pci.c b/src/southbridge/intel/bd82x6x/pci.c
index 85e431e619..f86d8a01e4 100644
--- a/src/southbridge/intel/bd82x6x/pci.c
+++ b/src/southbridge/intel/bd82x6x/pci.c
@@ -100,7 +100,7 @@ static void ich_pci_bus_enable_resources(struct device *dev)
 	ich_pci_dev_enable_resources(dev);
 }
 
-static void set_subsystem(device_t dev, unsigned vendor, unsigned device)
+static void set_subsystem(struct device *dev, unsigned vendor, unsigned device)
 {
 	/* NOTE: This is not the default position! */
 	if (!vendor || !device) {
diff --git a/src/southbridge/intel/bd82x6x/pcie.c b/src/southbridge/intel/bd82x6x/pcie.c
index 1f4c157f14..458729d0db 100644
--- a/src/southbridge/intel/bd82x6x/pcie.c
+++ b/src/southbridge/intel/bd82x6x/pcie.c
@@ -265,13 +265,13 @@ static void pci_init(struct device *dev)
 	}
 }
 
-static void pch_pcie_enable(device_t dev)
+static void pch_pcie_enable(struct device *dev)
 {
 	/* Power Management init before enumeration */
 	pch_pcie_pm_early(dev);
 }
 
-static void pch_pciexp_scan_bridge(device_t dev)
+static void pch_pciexp_scan_bridge(struct device *dev)
 {
 	struct southbridge_intel_bd82x6x_config *config = dev->chip_info;
 
@@ -306,7 +306,8 @@ static const char *pch_pcie_acpi_name(const struct device *dev)
 	return NULL;
 }
 
-static void pcie_set_subsystem(device_t dev, unsigned vendor, unsigned device)
+static void pcie_set_subsystem(struct device *dev, unsigned vendor,
+			       unsigned device)
 {
 	/* NOTE: This is not the default position! */
 	if (!vendor || !device) {
diff --git a/src/southbridge/intel/bd82x6x/sata.c b/src/southbridge/intel/bd82x6x/sata.c
index d4268da7c6..00a65c8659 100644
--- a/src/southbridge/intel/bd82x6x/sata.c
+++ b/src/southbridge/intel/bd82x6x/sata.c
@@ -208,7 +208,7 @@ static void sata_init(struct device *dev)
 	pch_iobp_update(0xea00408a, 0xfffffcff, 0x00000100);
 }
 
-static void sata_enable(device_t dev)
+static void sata_enable(struct device *dev)
 {
 	/* Get the chip configuration */
 	config_t *config = dev->chip_info;
@@ -233,7 +233,8 @@ static void sata_enable(device_t dev)
 	pci_write_config16(dev, 0x90, map);
 }
 
-static void sata_set_subsystem(device_t dev, unsigned vendor, unsigned device)
+static void sata_set_subsystem(struct device *dev, unsigned vendor,
+			       unsigned device)
 {
 	if (!vendor || !device) {
 		pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID,
@@ -249,7 +250,7 @@ static const char *sata_acpi_name(const struct device *dev)
 	return "SATA";
 }
 
-static void sata_fill_ssdt(device_t dev)
+static void sata_fill_ssdt(struct device *dev)
 {
 	config_t *config = dev->chip_info;
 	generate_sata_ssdt_ports("\\_SB_.PCI0.SATA", config->sata_port_map);
diff --git a/src/southbridge/intel/bd82x6x/smbus.c b/src/southbridge/intel/bd82x6x/smbus.c
index 339089054a..1754734f03 100644
--- a/src/southbridge/intel/bd82x6x/smbus.c
+++ b/src/southbridge/intel/bd82x6x/smbus.c
@@ -25,7 +25,7 @@
 #include <southbridge/intel/common/smbus.h>
 #include "pch.h"
 
-static void pch_smbus_init(device_t dev)
+static void pch_smbus_init(struct device *dev)
 {
 	struct resource *res;
 	u16 reg16;
@@ -41,7 +41,7 @@ static void pch_smbus_init(device_t dev)
 		outb(SMBUS_SLAVE_ADDR, res->base + SMB_RCV_SLVA);
 }
 
-static int lsmbus_read_byte(device_t dev, u8 address)
+static int lsmbus_read_byte(struct device *dev, u8 address)
 {
 	u16 device;
 	struct resource *res;
@@ -54,7 +54,7 @@ static int lsmbus_read_byte(device_t dev, u8 address)
 	return do_smbus_read_byte(res->base, device, address);
 }
 
-static int lsmbus_write_byte(device_t dev, u8 address, u8 val)
+static int lsmbus_write_byte(struct device *dev, u8 address, u8 val)
 {
 	u16 device;
 	struct resource *res;
@@ -72,7 +72,8 @@ static struct smbus_bus_operations lops_smbus_bus = {
 	.write_byte	= lsmbus_write_byte,
 };
 
-static void smbus_set_subsystem(device_t dev, unsigned vendor, unsigned device)
+static void smbus_set_subsystem(struct device *dev, unsigned vendor,
+				unsigned device)
 {
 	if (!vendor || !device) {
 		pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID,
@@ -87,7 +88,7 @@ static struct pci_operations smbus_pci_ops = {
 	.set_subsystem    = smbus_set_subsystem,
 };
 
-static void smbus_read_resources(device_t dev)
+static void smbus_read_resources(struct device *dev)
 {
 	struct resource *res = new_resource(dev, PCI_BASE_ADDRESS_4);
 	res->base = SMBUS_IO_BASE;
diff --git a/src/southbridge/intel/bd82x6x/usb_ehci.c b/src/southbridge/intel/bd82x6x/usb_ehci.c
index b5ce820b0f..7362dbd52e 100644
--- a/src/southbridge/intel/bd82x6x/usb_ehci.c
+++ b/src/southbridge/intel/bd82x6x/usb_ehci.c
@@ -74,7 +74,8 @@ static void usb_ehci_init(struct device *dev)
 	printk(BIOS_DEBUG, "done.\n");
 }
 
-static void usb_ehci_set_subsystem(device_t dev, unsigned vendor, unsigned device)
+static void usb_ehci_set_subsystem(struct device *dev, unsigned vendor,
+				   unsigned device)
 {
 	u8 access_cntl;
 
diff --git a/src/southbridge/intel/bd82x6x/usb_xhci.c b/src/southbridge/intel/bd82x6x/usb_xhci.c
index 6acc63bb91..1b2755b4ab 100644
--- a/src/southbridge/intel/bd82x6x/usb_xhci.c
+++ b/src/southbridge/intel/bd82x6x/usb_xhci.c
@@ -56,7 +56,8 @@ static const char *xhci_acpi_name(const struct device *dev)
 	return "XHC";
 }
 
-static void xhci_set_subsystem(device_t dev, unsigned vendor, unsigned device)
+static void xhci_set_subsystem(struct device *dev, unsigned vendor,
+			       unsigned device)
 {
 	if (!vendor || !device) {
 		pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID,
diff --git a/src/southbridge/intel/bd82x6x/watchdog.c b/src/southbridge/intel/bd82x6x/watchdog.c
index 74f69b032b..9a867e413a 100644
--- a/src/southbridge/intel/bd82x6x/watchdog.c
+++ b/src/southbridge/intel/bd82x6x/watchdog.c
@@ -28,7 +28,7 @@
   //
 void watchdog_off(void)
 {
-	device_t dev;
+	struct device *dev;
 	unsigned long value, base;
 
 	/* Turn off the ICH7 watchdog. */