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soc/intel/tigerlake: Update SerialIoUart settings for Tiger Lake 

update SerialIoUartAutoFlow settings for Tiger Lake platform.

BUG=none
BRANCH=none
TEST=Build and boot tigerlake rvp board

Signed-off-by: Srinidhi N Kaushik <srinidhi.n.kaushik@intel.com>
Change-Id: I5ff2c63857a868ca4ed72c6d93bf518e085b8879
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39169
Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com>
Reviewed-by: caveh jalali <caveh@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Srinidhi N Kaushik 2020-02-29 00:32:23 -08:00 committed by Patrick Georgi
parent fdccfc6267
commit 4af0adb443
1 changed files with 3 additions and 0 deletions
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3
src/soc/intel/tigerlake/fsp_params_tgl.c
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@ -13,6 +13,7 @@
* GNU General Public License for more details.
*/
#include <assert.h>
#include <console/console.h>
#include <device/device.h>
#include <device/pci.h>
@ -120,6 +121,8 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd)
/* PCH UART selection for FSP Debug */
params->SerialIoDebugUartNumber = CONFIG_UART_FOR_CONSOLE;
ASSERT(ARRAY_SIZE(params->SerialIoUartAutoFlow) > CONFIG_UART_FOR_CONSOLE);
params->SerialIoUartAutoFlow[CONFIG_UART_FOR_CONSOLE] = 0;
/* SATA */
dev = pcidev_on_root(PCH_DEV_SLOT_SATA, 0);