skylake boards: disable ACPI PM Timer

These devicetree patches set the ACPI PM Disabled variable to 1.
This will disable the ACPI PM timer and remove from FADT table.

BRANCH=none
BUG=chrome-os-partner:48646
TEST=Build for skylake board with the PmTimerDisabled policy in
devicetree set to 1.
iotools mmio_read32 0xfe0000fc should return 0x2.
cat /sys/devices/system/clocksource/clocksource0/available_clocksource
should list only "tsc hpet". acpi_pm should be removed from this list.

Change-Id: Ia66f37e13f0f2f527651418b8b5c337b56c25c7f
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: db3e8130495038850c7034b89701b4a5fcf88dce
Original-Change-Id: Ib1b876cfa361b8cbdde2f9e212e3da4fd724e498
Original-Signed-off-by: Archana Patni <archana.patni@intel.com>
Original-Signed-off-by: Subramony Sesha <subramony.sesha@intel.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/319362
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/13589
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

src/mainboard/google/chell/devicetree.cb

@@ -50,6 +50,7 @@ chip soc/intel/skylake
 	register "PmConfigSlpS4MinAssert" = "1"        # 1s
 	register "PmConfigSlpSusMinAssert" = "1"       # 500ms
 	register "PmConfigSlpAMinAssert" = "3"         # 2s
+	register "PmTimerDisabled" = "1"
 
 	# VR Settings Configuration for 5 Domains
 	#+----------------+-------+-------+-------------+-------------+-------+

src/mainboard/google/glados/devicetree.cb

@@ -50,6 +50,7 @@ chip soc/intel/skylake
 	register "PmConfigSlpS4MinAssert" = "1"        # 1s
 	register "PmConfigSlpSusMinAssert" = "1"       # 500ms
 	register "PmConfigSlpAMinAssert" = "3"         # 2s
+	register "PmTimerDisabled" = "1"
 
 	# VR Settings Configuration for 5 Domains
 	#+----------------+-------+-------+-------------+-------------+-------+

src/mainboard/google/lars/devicetree.cb

@@ -32,6 +32,7 @@ chip soc/intel/skylake
 	register "HeciEnabled" = "0"
 	register "SaGv" = "3"
 	register "FspSkipMpInit" = "1"
+	register "PmTimerDisabled" = "1"
 
 	# Enabling SLP_S3#, SLP_S4#, SLP_SUS and SLP_A Stretch
 	# SLP_S3 Minimum Assertion Width. Values 0: 60us, 1: 1ms, 2: 50ms, 3: 2s

src/mainboard/intel/kunimitsu/devicetree.cb

@@ -31,6 +31,7 @@ chip soc/intel/skylake
 	register "Device4Enable" = "1"
 	register "HeciEnabled" = "0"
 	register "SaGv" = "3"
+	register "PmTimerDisabled" = "1"
 
 	# Enabling SLP_S3#, SLP_S4#, SLP_SUS and SLP_A Stretch
 	# SLP_S3 Minimum Assertion Width. Values 0: 60us, 1: 1ms, 2: 50ms, 3: 2s