diff --git a/src/soc/amd/common/block/gpio_banks/Kconfig b/src/soc/amd/common/block/gpio_banks/Kconfig
index 1efb1db643..0a1bffee81 100644
--- a/src/soc/amd/common/block/gpio_banks/Kconfig
+++ b/src/soc/amd/common/block/gpio_banks/Kconfig
@@ -5,3 +5,16 @@ config SOC_AMD_COMMON_BLOCK_BANKED_GPIOS
 	  Select this option to use the newer style banks of GPIO signals.
 	  These are at offsets +0x1500, +0x1600, and +0x1700 from the AcpiMmio
 	  base.
+
+if SOC_AMD_COMMON_BLOCK_BANKED_GPIOS
+
+config SOC_AMD_COMMON_BLOCK_BANKED_GPIOS_NON_SOC_CODEBASE
+	bool
+	help
+	  Select this option when selecting the GPIO bank support from AMD
+	  chipsets outside the soc/ subtree that only support a subset of the
+	  features available on the chipsets inside the soc/ subtree. When this
+	  option is selected, no SMI or SCI event can be configured by the GPIO
+	  code.
+
+endif # SOC_AMD_COMMON_BLOCK_BANKED_GPIOS
diff --git a/src/soc/amd/common/block/gpio_banks/gpio.c b/src/soc/amd/common/block/gpio_banks/gpio.c
index 8f84cb67fc..b3c1ac1b72 100644
--- a/src/soc/amd/common/block/gpio_banks/gpio.c
+++ b/src/soc/amd/common/block/gpio_banks/gpio.c
@@ -171,8 +171,9 @@ static void set_single_gpio(const struct soc_amd_gpio *g)
 	static const struct soc_amd_event *gev_tbl;
 	static size_t gev_items;
 	int gevent_num;
-	const bool can_set_smi_flags = !(CONFIG(VBOOT_STARTS_BEFORE_BOOTBLOCK) &&
-			ENV_SEPARATE_VERSTAGE);
+	const bool can_set_smi_flags = !((CONFIG(VBOOT_STARTS_BEFORE_BOOTBLOCK) &&
+			ENV_SEPARATE_VERSTAGE) ||
+			CONFIG(SOC_AMD_COMMON_BLOCK_BANKED_GPIOS_NON_SOC_CODEBASE));
 
 	set_gpio_mux(g->gpio, g->function);
 
diff --git a/src/southbridge/amd/pi/hudson/Kconfig b/src/southbridge/amd/pi/hudson/Kconfig
index fa60d17654..c959e28301 100644
--- a/src/southbridge/amd/pi/hudson/Kconfig
+++ b/src/southbridge/amd/pi/hudson/Kconfig
@@ -18,6 +18,7 @@ config SOUTHBRIDGE_SPECIFIC_OPTIONS
 	select SOC_AMD_COMMON_BLOCK_ACPIMMIO
 	select SOC_AMD_COMMON_BLOCK_ACPIMMIO_BIOSRAM
 	select SOC_AMD_COMMON_BLOCK_BANKED_GPIOS
+	select SOC_AMD_COMMON_BLOCK_BANKED_GPIOS_NON_SOC_CODEBASE
 	select SOC_AMD_COMMON_BLOCK_PCI_MMCONF
 
 config EHCI_BAR