arch/x86: allow idt to be available to link in all stages
Add Kconfig IDT_IN_EVERY_STAGE to optionally specify having the interrupt handling code available to all stages. In order to do this the idt setup is moved to a C module. The vecX entries are made global so that a table of references to all the interrupt vector entry points can be used to dynamically initialize the idt. The ramification for ramstage is that exceptions are initialized later (lib/hardwaremain.c). Not all stages initialize exceptions when this Kconfig variable is selected, but bootblock for the C, stages using assembly_entry.S, and of course ramstage do. Anything left out just needs a call to exception_init() at the right location. BUG=b:72728953 Change-Id: I4146a040e5e43bed7ccc6cb0a7dc2271f1e7b7fa Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/25761 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
This commit is contained in:
Aaron Durbin
parent
e74ba1984d
commit
4b032e457f
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@ -302,3 +302,10 @@ config NUM_CAR_PAGE_TABLE_PAGES
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depends on PAGING_IN_CACHE_AS_RAM
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help
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The number of 4KiB pages that should be pre-allocated for page tables.
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# Provide the interrupt handlers to every stage. Not all
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# stages may take advantage.
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config IDT_IN_EVERY_STAGE
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bool
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default n
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depends on ARCH_X86
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@ -92,6 +92,8 @@ ifeq ($(CONFIG_ARCH_BOOTBLOCK_X86_32)$(CONFIG_ARCH_BOOTBLOCK_X86_64),y)
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bootblock-y += boot.c
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bootblock-y += cpu_common.c
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bootblock-$(CONFIG_IDT_IN_EVERY_STAGE) += exception.c
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bootblock-$(CONFIG_IDT_IN_EVERY_STAGE) += idt.S
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bootblock-y += memcpy.c
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bootblock-y += memset.c
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bootblock-$(CONFIG_COLLECT_TIMESTAMPS_TSC) += timestamp.c
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@ -169,6 +171,8 @@ endif # CONFIG_ARCH_BOOTBLOCK_X86_32 / CONFIG_ARCH_BOOTBLOCK_X86_64
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ifeq ($(CONFIG_ARCH_VERSTAGE_X86_32)$(CONFIG_ARCH_VERSTAGE_X86_64),y)
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verstage-y += boot.c
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verstage-$(CONFIG_IDT_IN_EVERY_STAGE) += exception.c
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verstage-$(CONFIG_IDT_IN_EVERY_STAGE) += idt.S
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verstage-$(CONFIG_ARCH_RAMSTAGE_X86_32) += cpu_common.c
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verstage-y += memset.c
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@ -206,6 +210,8 @@ romstage-y += cbmem.c
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romstage-y += cbfs_and_run.c
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romstage-$(CONFIG_ARCH_RAMSTAGE_X86_32) += cpu_common.c
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romstage-$(CONFIG_EARLY_EBDA_INIT) += ebda.c
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romstage-$(CONFIG_IDT_IN_EVERY_STAGE) += exception.c
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romstage-$(CONFIG_IDT_IN_EVERY_STAGE) += idt.S
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romstage-y += memcpy.c
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romstage-y += memmove.c
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romstage-y += memset.c
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@ -281,6 +287,8 @@ postcar-y += cbfs_and_run.c
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postcar-y += cbmem.c
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postcar-y += cpu_common.c
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postcar-$(CONFIG_EARLY_EBDA_INIT) += ebda.c
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postcar-$(CONFIG_IDT_IN_EVERY_STAGE) += exception.c
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postcar-$(CONFIG_IDT_IN_EVERY_STAGE) += idt.S
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postcar-y += exit_car.S
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postcar-y += memcpy.c
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postcar-y += memmove.c
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@ -343,6 +351,8 @@ ramstage-$(CONFIG_COOP_MULTITASKING) += thread_switch.S
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ramstage-$(CONFIG_COLLECT_TIMESTAMPS_TSC) += timestamp.c
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ramstage-$(CONFIG_HAVE_ACPI_RESUME) += wakeup.S
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smm-$(CONFIG_IDT_IN_EVERY_STAGE) += exception.c
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smm-$(CONFIG_IDT_IN_EVERY_STAGE) += idt.S
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smm-y += memcpy.c
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smm-y += memmove.c
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smm-y += memset.c
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@ -64,6 +64,9 @@ debug_spinloop:
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#endif
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andl $0xfffffff0, %esp
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#if IS_ENABLED(CONFIG_IDT_IN_EVERY_STAGE)
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call exception_init
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#endif
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call car_stage_entry
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/* This is here for linking purposes. */
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@ -81,28 +81,6 @@ _start:
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push $0
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push $0
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/* Initialize the Interrupt Descriptor table */
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leal _idt, %edi
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leal vec0, %ebx
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movl $(0x10 << 16), %eax /* cs selector */
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1: movw %bx, %ax
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movl %ebx, %edx
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movw $0x8E00, %dx /* Interrupt gate - dpl=0, present */
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movl %eax, 0(%edi)
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movl %edx, 4(%edi)
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addl $6, %ebx
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addl $8, %edi
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cmpl $_idt_end, %edi
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jne 1b
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/* Load the Interrupt descriptor table */
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#ifndef __x86_64__
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lidt idtarg
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#else
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// FIXME port table to x64 - lidt idtarg
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#endif
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/*
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* Now we are finished. Memory is up, data is copied and
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* bss is cleared. Now we call the main routine and
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@ -145,7 +123,7 @@ gdb_stub_breakpoint:
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jmp int_hand
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#endif
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.globl gdt, gdt_end, idtarg
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.globl gdt, gdt_end
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gdtaddr:
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.word gdt_end - gdt - 1
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@ -227,14 +205,6 @@ gdt:
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#endif
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gdt_end:
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idtarg:
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.word _idt_end - _idt - 1 /* limit */
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.long _idt
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.word 0
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_idt:
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.fill 20, 8, 0 # idt is uninitialized
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_idt_end:
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.section ".text._start", "ax", @progbits
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#ifdef __x86_64__
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SetCodeSelector:
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@ -11,8 +11,14 @@
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* GNU General Public License for more details.
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*/
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#include <arch/early_variables.h>
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#include <arch/exception.h>
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#include <commonlib/helpers.h>
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#include <compiler.h>
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#include <console/console.h>
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#include <console/streams.h>
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#include <rules.h>
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#include <stdint.h>
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#include <string.h>
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#if IS_ENABLED(CONFIG_GDB_STUB)
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@ -518,3 +524,109 @@ void x86_exception(struct eregs *info)
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die("");
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#endif
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}
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#define GATE_P (1 << 15)
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#define GATE_DPL(x) (((x) & 0x3) << 13)
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#define GATE_SIZE_16 (0 << 11)
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#define GATE_SIZE_32 (1 << 11)
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#define IGATE_FLAGS (GATE_P | GATE_DPL(0) | GATE_SIZE_32 | (0x6 << 8))
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struct intr_gate {
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uint16_t offset_0;
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uint16_t segsel;
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uint16_t flags;
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uint16_t offset_1;
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#if ENV_X86_64
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uint32_t offset_2;
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uint32_t reserved;
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#endif
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} __packed;
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/* Even though the vecX symbols are interrupt entry points just treat them
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like data to more easily get the pointer values in C. Because IDT entries
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format splits the offset field up one can't use the linker to resolve
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parts of a relecation on x86 ABI an array of pointers is used to gather
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the symbols. The IDT is initialized at runtime when exception_init() is
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called. */
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extern u8 vec0[], vec1[], vec2[], vec3[], vec4[], vec5[], vec6[], vec7[];
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extern u8 vec8[], vec9[], vec10[], vec11[], vec12[], vec13[], vec14[], vec15[];
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extern u8 vec16[], vec17[], vec18[], vec19[];
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static const uintptr_t intr_entries[] = {
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(uintptr_t)vec0, (uintptr_t)vec1, (uintptr_t)vec2, (uintptr_t)vec3,
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(uintptr_t)vec4, (uintptr_t)vec5, (uintptr_t)vec6, (uintptr_t)vec7,
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(uintptr_t)vec8, (uintptr_t)vec9, (uintptr_t)vec10, (uintptr_t)vec11,
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(uintptr_t)vec12, (uintptr_t)vec13, (uintptr_t)vec14, (uintptr_t)vec15,
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(uintptr_t)vec16, (uintptr_t)vec17, (uintptr_t)vec18, (uintptr_t)vec19,
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};
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static struct intr_gate idt[ARRAY_SIZE(intr_entries)] __aligned(8) CAR_GLOBAL;
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static inline uint16_t get_cs(void)
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{
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uint16_t segment;
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asm volatile (
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"mov %%cs, %0\n"
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: "=r" (segment)
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:
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: "memory"
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);
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return segment;
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}
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struct lidtarg {
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uint16_t limit;
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#if ENV_X86_32
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uint32_t base;
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#else
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uint64_t base;
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#endif
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} __packed;
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/* This global is for src/cpu/x86/lapic/secondary.S usage which is only
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used during ramstage. */
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struct lidtarg idtarg;
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static void load_idt(void *table, size_t sz)
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{
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struct lidtarg lidtarg = {
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.limit = sz - 1,
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.base = (uintptr_t)table,
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};
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asm volatile (
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"lidt %0"
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:
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: "m" (lidtarg)
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: "memory"
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);
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if (ENV_RAMSTAGE)
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memcpy(&idtarg, &lidtarg, sizeof(idtarg));
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}
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asmlinkage void exception_init(void)
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{
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int i;
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uint16_t segment;
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struct intr_gate *gates = car_get_var_ptr(idt);
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segment = get_cs();
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gates = car_get_var_ptr(idt);
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/* Initialize IDT. */
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for (i = 0; i < ARRAY_SIZE(idt); i++) {
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gates[i].offset_0 = intr_entries[i];
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gates[i].segsel = segment;
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gates[i].flags = IGATE_FLAGS;
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gates[i].offset_1 = intr_entries[i] >> 16;
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#if ENV_X86_64
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gates[i].offset_2 = intr_entries[i] >> 32;
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#endif
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}
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load_idt(gates, sizeof(idt));
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}
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@ -17,7 +17,8 @@
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#else
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.code32
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#endif
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.global vec0
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.global vec0, vec1, vec2, vec3, vec4, vec5, vec6, vec7, vec8, vec9
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.global vec10, vec11, vec12, vec13, vec14, vec15, vec16, vec17, vec18, vec19
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vec0:
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push $0 /* error code */
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push $0 /* vector */
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@ -30,6 +30,13 @@
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#ifndef _ARCH_EXCEPTION_H
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#define _ARCH_EXCEPTION_H
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#include <arch/cpu.h>
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#include <rules.h>
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#if IS_ENABLED(CONFIG_IDT_IN_EVERY_STAGE) || ENV_RAMSTAGE
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asmlinkage void exception_init(void);
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#else
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static inline void exception_init(void) { /* not implemented */ }
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#endif
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#endif
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