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soc/intel/cmn/cse: Drop redundant macro check for heci1_disable() 

This patch removes redundant DISABLE_HECI1_AT_PRE_BOOT config check for
heci1_disable(), once by caller (from various SoC) and again inside the
callee (heci1_disable) function.

As all callers of heci1_disable() function are doing
DISABLE_HECI1_AT_PRE_BOOT config enabled check, hence, the second check
inside the callee can be dropped.

BUG=b:228789015
TEST=Able to build and boot google/redrix with this change. CSE PCI
device is getting function disabled upon selecting
DISABLE_HECI1_AT_PRE_BOOT from SoC config.

Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: I47d7a9989e355987618d089f79c3340fcf4953ad
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63821
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
This commit is contained in:
Subrata Banik 2022-04-25 15:28:19 +05:30 committed by Felix Held
parent c176fc2dfb
commit 4b1f4e3a99
1 changed files with 0 additions and 3 deletions
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3
src/soc/intel/common/block/cse/disable_heci.c
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@ -83,9 +83,6 @@ static void heci1_disable_using_sbi(void)
void heci1_disable(void)
{
if (!CONFIG(DISABLE_HECI1_AT_PRE_BOOT))
return;
if (ENV_SMM && CONFIG(SOC_INTEL_COMMON_BLOCK_HECI1_DISABLE_USING_SBI)) {
printk(BIOS_INFO, "Disabling Heci using SBI in SMM mode\n");
return heci1_disable_using_sbi();