soc/intel/tigerlake: Allow devicetree to fill UPD related to TCSS OC

We need to change OC pin for type C USB3 ports and it depends
on the board design. Allowing it to be filled by devicetree will
make it easier to change the mapping based on the board design.

BUG=b:184660529
TEST="emerge-volteer coreboot" compiles without error.

Change-Id: I5058a18b1f4d11701cebbba85734fbc279539e52
Signed-off-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/54075
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>

src/soc/intel/tigerlake/chip.h

@@ -177,6 +177,8 @@ struct soc_intel_tigerlake_config {
 	uint16_t usb3_wake_enable_bitmap;
 	/* PCH USB2 PHY Power Gating disable */
 	uint8_t usb2_phy_sus_pg_disable;
+	/* Program OC pins for TCSS */
+	struct tcss_port_config tcss_ports[MAX_TYPE_C_PORTS];
 
 	/*
 	 * Acoustic Noise Mitigation

src/soc/intel/tigerlake/fsp_params.c

@@ -269,6 +269,12 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd)
 	memcpy(params->PcieRpClkReqDetect, config->PcieRpClkReqDetect,
 		sizeof(config->PcieRpClkReqDetect));
 
+	for (i = 0; i < ARRAY_SIZE(config->tcss_ports); i++) {
+		if (config->tcss_ports[i].enable)
+			params->CpuUsb3OverCurrentPin[i] =
+					config->tcss_ports[i].ocpin;
+	}
+
 	/* Enable xDCI controller if enabled in devicetree and allowed */
 	dev = pcidev_path_on_root(PCH_DEVFN_USBOTG);
 	if (dev) {

src/soc/intel/tigerlake/include/soc/usb.h

@@ -137,4 +137,19 @@ struct usb3_port_config {
 	.tx_downscale_amp = 0x00, \
 }
 
+struct tcss_port_config {
+	uint8_t enable;
+	uint8_t ocpin;
+};
+
+#define TCSS_PORT_EMPTY { \
+	.enable           = 0, \
+	.ocpin            = OC_SKIP, \
+}
+
+#define TCSS_PORT_DEFAULT(pin) { \
+	.enable           = 1, \
+	.ocpin            = (pin), \
+}
+
 #endif